University LSI Design Contest
The University LSI Design Contest has been conceived as a unique program at ASP-DAC. The purpose of the contest is to encourage research in LSI design at universities and its realization on a chip by providing opportunities to present and discuss the innovative and state-of-the-art design. The scope of the contest covers circuit techniques for (1) Analog / RF / Mixed-Signal Circuits, (2) Digital Signal Processer, (3) Microprocessors, and (4) Custom Application Specific Circuits / Memories, and methodologies for (a) Full-Custom / Cell-Based LSIs, (b) Gate Arrays, and (c) Field Programmable Devices.
This year, the University LSI Design Contest Committee received 19 designs from three countries/areas, and selected 16 designs out of them. The selected designs will be disclosed in pre-recorded presentations and real-time on-line QA sessions are scheduled at Session 1A and 2A, January 18. For two outstanding designs, The Best Design Award and The Special Feature Award will be presented in the opening session. We sincerely acknowledge the other contributions to the contest, too. It is our earnest belief to promote and enhance research and education in LSI design in academic organizations. Please join the University LSI Design Contest and enjoy the stimulating discussions.
- Date: Tuesday, January 19, 2021
- Time (Live chat Q&A): 15:00 - 15:30 (Session 1A), 15:30 - 16:00 (Session 2A)
- Co-chairs: Kousuke Miyaji (Shinshu University, Japan), Akira Tsuchiya (The University of Shiga Prefecture)
- University LSI design contest committee
- UDC Session Schedule I and II (html-version)
Title | |
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1A-1 | A DSM-based Polar Transmitter with 23.8% System Efficiency |
1A-2 | A 0.41W 34Gb/s 300GHz CMOS Wireless Transceiver |
1A-3 | Capacitive Sensor Circuit with Relative Slope-Boost Method Based on a Relaxation Oscillator |
1A-4 | 28GHz Phase Shifter with Temperature Compensation for 5G NR Phased-array Transceiver |
1A-5 | An up to 35 dBc/Hz Phase Noise Improving Design Methodology for Differential-Ring-Oscillators applied in Ultra-Low Power Systems |
1A-6 | Gate Voltage Optimization in Capacitive DC-DC Converters for Thermoelectric Energy Harvesting |
1A-7 | An 0.57 GOPS/DSP Object Detection PIM Acceleratoron FPGA |
1A-8 | Supply Noise Reduction Filter for Parallel Integrated Transimpedance Amplifiers |
2A-1 | A 65nm CMOS Process Li-ion Battery Charging Cascode SIDO Boost Converter with 89% Maximum Efficiency for RF Wireless Power Transfer Receiver |
2A-2 | A High-Accuracy Phase and Amplitude Detection Circuit for Calibration of 28GHz Phased Array Beamformer System |
2A-3 | A Highly Integrated Energy-efficient CMOS Millimeter-wave Transceiver with Direct-modulation Digital Transmitter, Quadrature Phased-coupled Frequency Synthesizer and Substrate-Integrated Waveguide E-shaped Patch Antenna |
2A-4 | A 3D-Stacked SRAM Using Inductive Coupling Technology for AI Inference Accelerator in 40-nm CMOS |
2A-5 | Sub-10-μm Coil Design for Multi-Hop Inductive Coupling Interface |
2A-6 | Current-Starved Chaotic Oscillator Over Multiple Frequency Decades on Low-Cost CMOS |
2A-7 | TCI tester: Tester for Through Chip Interface |
2A-8 | An 18 Bit Time-to-Digital Converter Design with Large Dynamic Range and Automated Multi-Cycle Concept |