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The 16th Asia and South Pacific Design Automation Conference

Session 7A  System Level Analysis and Optimization
Time: 10:20 - 12:20 Friday, January 28, 2011
Location: Room 411+412
Chairs: Hiroshi Saito (Aizu Univ., Japan), Lovic Ganchier (Kyushu Univ., Japan)

7A-1 (Time: 10:20 - 10:50)
TitleA Polynomial-Time Custom Instruction Identification Algorithm Based on Dynamic Programming
Author*Junwhan Ahn, Imyong Lee, Kiyoung Choi (Seoul National Univ., Republic of Korea)
Pagepp. 573 - 578
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7A-2 (Time: 10:50 - 11:20)
TitleExploring the Fidelity-Efficiency Design Space using Imprecise Arithmetic
Author*Jiawei Huang, John Lach (Univ. of Virginia, U.S.A.)
Pagepp. 579 - 584
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7A-3 (Time: 11:20 - 11:50)
TitleThroughput Optimization for Latency-Insensitive System with Minimal Queue Insertion
AuthorJuinn-Dar Huang, *Yi-Hang Chen, Ya-Chien Ho (National Chiao Tung Univ., Taiwan)
Pagepp. 585 - 590
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7A-4 (Time: 11:50 - 12:20)
TitleA Fast and Effective Dynamic Trace-based Method for Analyzing Architectural Performance
Author*Yi-Siou Chen, Lih-Yih Chiou, Hsun-Hsiang Chang (National Cheng Kung Univ., Taiwan)
Pagepp. 591 - 596
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