Preparation Guide for Technical Paper Submission

Deadline

The submission deadlines are set based on Japan Standard Time (JST). JST goes ahead of most other local times. The deadline by local times is as follows:

  • July 19 03:00 @ San Jose
  • July 19 06:00 @ New York
  • July 19 11:00 @ London
  • July 19 10:00 @ Paris, Munich
  • July 19 13:30 @ New Delhi
  • July 19 16:00 @ Beijing, Taipei
  • July 19 17:00 @ Tokyo, Seoul
  • July 19 18:00 @ Sydney

Key Dates:

  • Deadline for submission: July 19 (Mon), 2010 (17:00, JST)
  • Notification of acceptance: September 24 (Fri), 2010
  • Deadline for final version: November 15 (Mon), 2010 (17:00, JST)

Instructions

In order to submit your paper, please follow the instructions below.

1) Paper preparation

  • Initial manuscripts should NOT include authors' names and their affiliations in order to perform a blind review. Authors' names, their affiliations and the contact person are requested when you submit your paper via the paper submission system.

  • The paper should be between 3 to 6 pages in length including all figures, tables and references. The technical expositions will be reviewed by specialists but should include an introduction for nonspecialists that describes the problem and achieved results, focusing on the important ideas and their significance.

  • Accepted file format is PDF only. No other formats will be accepted. You must make a pdf file which can be read by Acrobat Reader 5.0. Manuscripts should not include special fonts such as Asian fonts.

  • The paper for initial submission is to be formated like this (LaTex, LaTex2e). You can get the templates of initial sumission for (LaTex), (LaTex2e), and (MSWord).

2) Paper Submission

Requirement

  • All accepted papers should be presented at the conference.
  • Dual submission with other conferences is not allowed.

Remarks:

  • Papers will be accepted for publication as either of regular papers or short papers. The paper type ** cannot ** be chosen by authors when submitting papers.
  • Papers may need to be shortened after acceptance, depending on the paper type. The page limit for short papers will be four.
  • The page limit for regular papers is 6 pages. For the camera-ready version up to 2 extra pages (maximum 8 pages) are allowed with extra payment.
  • Any modification in authors' names including the order of the listed authors after submission deadline is not allowed except that TPC approves the modification.


Areas of Interest:

Original papers on, but not limited to, the following areas are invited. Please note that ASP-DAC will work cooperatively with other conferences and symposia in the field to check for double submissions.

[1] System-Level Modeling and Simulation/Verification:
System-level modeling, specification, language, performance analysis, system-level simulation/verification, hardware-software co-simulation/co-verification, etc.
[2] System-Level Synthesis and Optimization:
System-on-chip and multi-processor SoC (MPSoC) design methodology, hardware-software partitioning, hardware-software co-design, IP/platform-based design, application-specific instruction-set processor (ASIP) synthesis, low power system design, etc.
[3] System-Level Memory/Communication Design and Networks on Chip:
Communication-based architecture design, network-on-chip (NoC) design methodologies and CAD, interface synthesis, system communication architecture, memory architecture, low power communication design, etc.
[4] Embedded and Real-Time Systems:
Embedded system design, real-time system design, OS, middleware, compilation techniques, memory/cache optimization, interfacing and software issues.
[5] High-Level/Behavioral/Logic Synthesis and Optimization:
High-Level/behavioral/RTL synthesis, technology-independent optimization, technology mapping, interaction between logic design and layout, sequential and asynchronous logic synthesis, resource scheduling, allocation, and synthesis.
[6] Validation and Verification for Behavioral/Logic Design:
Logic simulation, symbolic simulation, formal verification, equivalence checking, transaction-level/RTL and gate-level modeling and validation, assertion-based verification, coverage-analysis, constrained-random testbench generation.
[7] Physical Design:
Floorplanning, partitioning, placement, buffer insertion, routing, interconnect planning, clock network synthesis, post-placement optimization, layout verification, package/PCB routing, etc.
[8] Timing, Power, Thermal Analysis and Optimization:
Deterministic and statistical static timing analysis, statistical performance analysis and optimization, low power design, power and leakage analysis, power/ground and package analysis and optimization, thermal analysis, etc.
[9] Signal/Power Integrity, Interconnect/Device/Circuit Modeling and Simulation:
Signal/power integrity, clock and bus analysis, interconnect and substrate modeling/extraction, package modeling, device modeling/simulation, circuit simulation, high-frequency and electromagnetic simulation of circuits, etc.
[10] Design for Manufacturability/Yield and Statistical Design:
DFM, DFY, CAD support for OPC and RET, variability analysis, yield analysis and optimization, reliability analysis, design for resilience and robustness, cell library design, design fabrics, etc.
[11] Test and Design for Testability:
Testable design, fault modeling, ATPG, BIST and DFT, memory test and repair, core and system test, delay test, analog and mixed signal test.
[12] Analog, RF and Mixed Signal Design and CAD:
Analog/RF synthesis, analog layout, verification and simulation techniques, noise analysis, mixed-signal design considerations.
[13] Emerging technologies and applications
i. Design case studies for emerging applications: multimedia, consumer electronics, communication, networking, ubiquitous computing and biomedical applications, etc.
ii. Post CMOS technologies: nanotechnology, quantum, optical interconnect, 3D integration, probabilistic architecture, microfluidics, molecular, bioelectronics, etc., with emphasis on modeling, analysis, novel circuit/architecture, CAD tools, and design methodologies.

Inquiry

For more information, please contact: aspdac2011-tpc [at] mls.aspdac.com

Last Updated on: 2010年6月22日