University LSI Design Contest
The University LSI Design Contest was conceived as a unique program of ASP-DAC Conference. The purpose of the Contest is to encourage education and research in LSI design, and its realization on chips at universities, and other educational organizations by providing opportunities to present and discuss innovative and state-of-the-art designs at the conference. Application areas and types of circuits include (1) Analog, RF and Mixed-Signal Circuits, (2) Digital Signal processing, (3) Microprocessors, and (4) Custom Application Specific Circuits and Memories. Methods or technology used for implementation include (a) Full Custom and Cell-Based LSIs, (b) Gate Arrays, and (c) Field Programmable Devices, including FPGA/PLDs. This year, 26 selected designs from five countries/areas will be disclosed in Session 1D with short presentations followed by live discussions in front of posters with light meals. Submitted designs were reviewed by the members of the University Design Contest Committee. As a result, the 26 designs were selected. Also, we have instituted The Best Design Award and The Special Feature Award.
It is with great pleasure that we acknowledge the contributions to the Design Contest, and it is our earnest belief that it will promote and enhance research and education in LSI design in academic organizations. It is also our hope that many people not only in academia but in industry will attend the contest and enjoy the stimulating discussions.
- Date: Wednesday, January 26, 2011
- Place: Pacifico Yokohama, Conference Center, 4F
- Oral Presentation : Room 416+417 (10:20-12:20)
- Poster Presentation : Room 418 [Food will be served] (12:20-13:40)
- Co-chairs : Masanori Hariyama (Tohoku University, Japan), Hiroshi Kawaguchi (Kobe University, Japan)
- University LSI design contest committee
Time | Title | |
---|---|---|
1D-1 | 10:20 - 10:24 | A H.264/MPEG-2 Dual Mode Video Decoder Chip Supporting Temporal/Spatial Scalable Video |
1D-2 | 10:24 - 10:28 | A Gate-level Pipelined 2.97GHz Self Synchronous FPGA in 65nm CMOS |
1D-3 | 10:28 - 10:32 | A 4.32 mm2 170mW LDPC Decoder in 0.13um CMOS for WiMax/Wi-Fi Applications |
1D-4 | 10:32 - 10:36 | All-Digital PMOS and NMOS Process Variability Monitor Utilizing Buffer Ring with Pulse Counter |
1D-5 | 10:36 - 10:40 | Jitter Amplifier for Oscillator-Based True Random Number Generator |
1D-6 | 10:40 - 10:44 | A 65nm Flip-Flop Array to Measure Soft Error Resiliency against High-Energy Neutron and Alpha Particles |
1D-7 | 10:44 - 10:48 | Dual-Phase Pipeline Circuit Design Automation with a Built-in Performance Adjusting Mechanism |
1D-8 | 10:48 - 10:52 | Geyser-2: The Second Prototype CPU with Fine-grained Run-time Power Gating |
1D-9 | 10:52 - 10:56 | An Implementation of an Asynchronous FPGA Based on LEDR/Four-Phase-Dual-Rail Hybrid Architecture |
1D-10 | 10:56 - 11:00 | Design and Chip Implementation of a Heterogeneous Multi-core DSP |
1D-11 | 11:00 - 11:04 | A Low-Power Management Technique for High-Performance Domino Circuits |
1D-12 | 11:04 - 11:08 | Design and Evaluation of Variable Stages Pipeline Processor Chip |
1D-13 | 11:08 - 11:12 | TurboVG: A HW/SW Co-Designed Multi-Core OpenVG Accelerator for Vector Graphics Applications with Embedded Power Profiler |
1D-14 | 11:12 - 11:16 | Design and Implementation of a High Performance Closed-Loop MIMO Communications with Ultra Low Complexity Handset |
1D-15 | 11:16 - 11:20 | A 58-63.6GHz Quadrature PLL Frequency Synthesizer Using Dual-Injection Technique |
1D-16 | 11:20 - 11:24 | An Ultra-low-voltage LC-VCO with a Frequency Extension Circuit for Future 0.5-V Clock Generation |
1D-17 | 11:24 - 11:28 | A 32Gbps Low Propagation Delay 4x4 Switch IC for Feedback-Based System in 0.13um CMOS Technology |
1D-18 | 11:28 - 11:32 | A Fully Integrated Shock Wave Transmitter with an On-Chip Dipole Antenna for Pulse Beam-Formability in 0.18-um CMOS |
1D-19 | 11:32 - 11:36 | An On-Chip Characterizing System for Within-Die Delay Variation Measurement of Individual Standard Cells in 65-nm CMOS |
1D-21 | 11:40 - 11:44 | Robust and Efficient Baseband Receiver Design for MB-OFDM UWB System |
1D-22 | 11:44 - 11:48 | A 95-nA, 523ppm/C, 0.6-uW CMOS Current Reference Circuit with Subthreshold MOS Resistor Ladder |
1D-23 | 11:48 - 11:52 | A 80-400 MHz 74 dB-DR Gm-C Low-Pass Filter With a Unique Auto-Tuning System |
1D-24 | 11:52 - 11:56 | An Adaptively Biased Low-Dropout Regulator with Transient Enhancement |
1D-25 | 11:56 - 12:00 | A Low-Power Triple-Mode Sigma-Delta DAC for Reconfigurable (WCDMA/TD-SCDMA/GSM) Transmitters |
1D-26 | 12:00 - 12:04 | A Simple Non-coherent Solution to the UWB-IR Communication |