Designers' Forum

Designers' Forum is conceived as a unique program that shares the design experience and solutions of real product developments among LSI designers and EDA academia/developers. It consists of these four special sessions:

  • Date: January 27-28, 2011
  • Place: Pacifico Yokohama, Conference Center, 4F, Room 416+417
  • Designers' Forum Chair: Kunio Uchiyama (Hitachi Ltd.)
  • Designers' Forum Co-Chair: Makoto Nagata (Kobe Univ., Japan)

Date/Time Title
5D January 27 / 13:40 - 15:40 Panel Discussion:
C-P-B co-design/co-verification technology for DDR3 1.6G in consumer products
6D January 27 / 16:00 - 18:00 Oral Session:
Emerging technologies for wellness applications
8D January 28 / 13:40 - 15:40 Oral Session:
State-of-The-Art SoCs and Its Design Methodology
9D January 28 / 16:00 - 18:00 Panel Discussion:
Advanced packaging and 3D Technologies

Designs will be presented focusing mainly on the design styles, problems and ways to tackle these. Panel discussions will also be held concerning the latest design problems. The following gives detailed information of each session.
It should also be noticed that the topics of sessions 5D and 8D are closely relevant to the special stages of a collocated EDS (Electronic Design and Solution) Fair.

Session 5D: Thursday, January 27, 13:40-15:40, Room 416+417

Panel Discussion: C-P-B co-design/co-verification technology for DDR3 1.6G in consumer products

Chip-package-board co-design/co-verification techniques for coming DDR3 1.6-Gbps interface for consumer applications will be discussed. Such high-data rate needs to be realized with low-cost assembly like wire bonding on a FR-4 board with small number of layers. The panelists will be solicited from a set maker, a semiconductor manufacturer, an IP provider, a tool vendor, and assembly foundary.

Organizer:Koji Kato (Sony, Japan)
Moderator:Makoto Nagata (Kobe Univ., Japan)
Panelists: Keisuke Matsunami(Senior Manager,Distinguished Engineer, Sony, Japan)
Yoshinori Fukuba(Chief Specialist, Toshiba, Japan)
Ji Zheng(Director, Chip Package System, Apache Design Solutions, USA)
Jen-Tai Hsu(Senior Director, Global Unichip Corporation, USA)
CT Chiu(Director of corporate R&D, ASE, Taiwan)

Session 6D: Thursday, January 27, 16:00-18:00, Room 416+417

Oral Session: Emerging technologies for wellness applications

Wellness opens a new field of VLSI systems. Biological information sensing and systems-on-a-chip (SoC) design for medical applications will be overviewed by Prof. Imai of Osaka Univ. An ultra low power design of a micro controller with supporting digital processing elements specifically applicable to medical applications will be given by TI. Wireless autonomous solutions for sensing human body and their system level design consideration will be discussed by IMEC. Hitachi will disclose a wearable badge-shaped sensor and feedback system that motivates workers and improves individual productivity.

Organizer: Hideki Yoshizawa (Fujitsu Labs., Japan)

  • 6D-1 : Biological Information Sensing Technologies for Medical, Health Care, and Wellness Applications
    - Masaharu Imai, Yoshinori Takeuchi, Keishi Sakanushi, and Hirofumi Iwato (Osaka University, Japan)
  • 6D-2 : Ultra-Low Power Microcontrollers for Portable, Wearable, and Implantable Medical Electronics
    - Srinivasa R. Sridhara (Texas Instruments, USA)
  • 6D-3 : Human++: wireless autonomous sensor technology for body area networks
    - Pop Valer (IMEC, Netherland)
  • 6D-4 : Healthcare of an Organization: Using Wearable Sensors and Feedback System for Energizing Workers
    - Koji Ara, Tomoaki Akitomi, Nobuo Sato, Satomi Tsuji, Miki Hayakawa, Yoshihiro Wakisaka, Norio Ohkubo, Rieko Otsuka, Fumiko Beniyama, Norihiko Moriwaki, and Kazuo Yano (Hitachi, Japan)

Session 8D: Friday, January 28, 13:40-15:40, Room 416+417

Oral Session: State-of-The-Art SoCs and Design Methodologies

Most advanced systems-on-a-chip (SoC) realization of digital electronics will be presented by Panasonic and Toshiba, followed by state-of-the-art design methodologies for such SoCs from Fujitsu, Renesas, and Semiconductor Technology Academic Research Center (STARC). Topics in this session cover 3D-TV systems and related SoC integration (Panasonic), a mobile application processor with the capability of H.264 full HD in stacked SoC integration (Toshiba), analysis of fine-grained power managements in low-power SoC design (Fujitsu), prototyping techniques supporting System-C design of a full HD digital TV SoC chip (Renesas), and an integrated RTL-to-GDS physical design flow toward 32 nm/28nm technology nodes (STARC).

Organizer: Masaitsu Nakajima (Panasonic, Japan)

  • 8D-1 : Advanced System LSIs for Home 3D System
    - Takao Suzuki (Panasonic Corporation, Japan)
  • 8D-2 : Development of Low Power and High Performance Application Processor (T6G) for Multimedia Mobile Applications
    - Yoshiyuki Kitasho, Yu Kikuchi, Takayoshi Shimazawa, Yasuo Ohara, Masafumi Takahashi, Yoshio Masubuchi, Yukihito Oowaki (Toshiba Corporation, Japan)
  • 8D-3 : Design Constraint of Fine Grain Supply Voltage Control LSI
    - Atsuki Inoue (Fujitsu Laboratories Ltd., Japan)
  • 8D-4 : FPGA Prototyping using Behavioral Synthesis for Improving Video Processing Algorithm and FHD TV SoC Design
    - Masaru Takahashi (Renesas Electronics Corporation, Japan)
  • 8D-5 : An RTL-to-GDS2 Design Methodology for Advanced System LSI
    - Nobuyuki Nishiguchi (Semiconductor Technology Academic Research Center (STARC), Japan)

Session 9D: Friday, January 28, 16:00-18:00, Room 416+417

Panel Discussion: Advanced packaging and 3D Technologies

3D packaging is a key technology to satisfy a growing demand to realize highly integrated system and memory. The panel session explores the technologies of three dimensional stacked chips and discusses the challenges to design and test of such integrated chips. The panelists globally come from IMEC, Toshiba, IBM, J-Devices, and Cadence.

Organizer:Yoshio Masubuchi (Toshiba, Japan)
Moderator:Kenichi Osada (Hitachi, Japan)
Panelists: Geert Van der Plas (Principal scientist, IMEC, Belgium)
Hirokazu Ezawa (Chief Specialist, Toshiba, Japan)
Yasumitsu Orii (Senior Technical Staff Member, IBM, Japan)
Yoichi Hiruta (Chief Technology Officer, J-Devices, Japan)
Chris Cheung (Engineering Director, Cadence Design Systems, USA)

Last Updated on: 1 16, 2011