Technical Program Committee

Technical Program Chair

Hyunchul Shin (Hanyang Univ., Korea)

Technical Program Vice Chair

Yao-Wen Chang (National Taiwan Univ., Taiwan)

Nozomu Togawa (Waseda Univ., Japan)

Secretary

Youngsoo Shin (KAIST, Korea)

Yungseon Eo (Hanyang Univ., Korea)

Sub committees and sub committee chairs

* : subcommittee chairs
[01] System-Level Modeling and Simulation/Verification
* Ing-Jer Huang (National Sun-Yat-Sen Univ., Taiwan)
Byeong Min (Samsung, Korea)
Chia-Lin Yang (National Taiwan Univ., Taiwan)
Nagisa Ishiura (Kwansei Gakuin Univ., Japan)
Joerg Henkel (Univ. of Karlsruhe, Germany)
[02] System-Level Synthesis and Optimization
* Yuichi Nakamura (NEC, Japan)
Li Shang (Univ. of Colorado, USA)
Danella Zhao (Univ. of Louisiana at Lafayette, USA)
Tsuyoshi Isshiki (Tokyo Institute of Technology, Japan)
Jen-Chieh Yeh (ITRI, Taiwan)
Hiroshi Saito (Aizu Univ. , Japan)
Masanori Murooka (Tohoku Univ., Japan)
[03] System-Level Memory/Communication Design and Networks on Chip
* Yuan Xie (Pennsylvania State Univ., USA)
Hiroyuki Tomiyama (Nagoya Univ., Japan)
Yoshinori Takeuchi (Osaka Univ., Japan)
Michihiro Koibuchi (National Institute of Informatics, Japan)
Yunheung Paek (Seoul National Univ., Korea)
Yu Wang (Tsinghua Univ., China)
Jiang Xu (Hongkong Univ. of Science and Technology, Hongkong)
David Atienza (EPFL, Switzerland)
Fabien Clermidy (CEA-LETI, France)
[04] Embedded and Real-Time Systems
* Naehyuck Chang (Seoul National Univ., Korea)
Samarjit Chakraborty (Technical Univ. of Munich, Germany)
Zili?Shao? (Hong Kong Polytechnic Univ., China)
Pai Chou (UC Irvine, USA)
Jian-Jia Chen (Karlsruhe Institue of Technology, Germany)
Yiran Chen (Seagate, USA)
Prabhat Mishra (Univ. of Florida, USA)
Sangsoo Park (Ewha Womans Univ., Korea)
Eli Bozorgzadeh (UC Irvine, USA)
Dongwan Shin (Qualcomm, USA)
[05] High-Level/Behavioral/Logic Synthesis and Optimization
* Deming Chen (Univ. of Illinois at Urbana-Champaign, USA)
Kiyoung Choi (Seoul National Univ., Korea)
Rolf Drechsler (Univ. of Bremen, Germany)
Hiroyuki Higuchi (Fujitsu Laboratories, Japan)
Ani Nahapetian (UC Los Angeles, USA)
M.B. Srinivas (International Institute of Information Technology, India)
Chun-Yao Wang (National Tsing Hua Univ., Taiwan)
Shigeru Yamashita (Ritsumeikan Univ., Japan)
[06] Validation and Verification for Behavioral/Logic Design
* Shin-ichi Minato (Hokkaido Univ., Japan)
Yoshinori Watanabe (Cadence, USA)
Kiyoharu Hamaguchi (Osaka Univ., Japan)
Chung-Yang Huang (National Taiwan Univ., Taiwan)
Miroslav Velev (Aries Design Automation, USA)
In-Ho Moon (Synopsys, USA)
[07] Physical Design
* David Z. Pan (Univ. of Texas at Austin, USA)
Shabbir Batterywala (Synopsys, India)
Sheqin Dong (Tsinghua Univ., China)
Jeong-Tyng Li (SpringSoft, USA)
Yih-Lang Li (National Chiao Tung Univ., Taiwan)
Wai Kei Mak (National Tsinghua Univ., Taiwan)
Cliff Sze (IBM, USA)
Yasuhiro Takashima (Univ. of Kitakyushu, Japan)
Lingli Wang (Fudan Univ., China)
Lihong Zhang (Memorial Univ., Canada)
[08] Timing, Power Thermal Analysis and Optimization
* Sachin Sapatnekar (Univ. of Minnesota, USA)
Shih-Hsu Huang (Chung Yuan Christian Univ., Taiwan)
Kimiyoshi Usami (Shibaura Institute of Technology, Japan)
Massimo Poncino (Politecnico di Torino, Italy)
Azadeh Davoodi (Univ. of Wisconsin, USA)
Bong-Hyun Lee (Samsung, Korea)
Lei He (UC Los Angeles, USA)
Yuchun Ma (Tsinghua Univ., China)
Masanori Hashimoto (Osaka Univ., Japan)
Seong-Ook Jung (Yonsei Univ., Korea)
[09] Signal/Power Integrity, Interconnect/Device/Circuit Modeling and Simulation
* Yungseon Eo (Hanyang Univ., Korea)
Kimihiro Ogawa (STARC, Japan)
Yu-Min Roger Lee (National Chiao Tung Univ., Taiwan)
Zuochang Ye (Tsinghua Univ., China)
Sungroh Yoon (Korea Univ., Korea)
Kyu-won Ken Choi (Illinois Institute of Technology, USA)
Ram Archar (Carleton Univ., Canada)
[10] Design for Manufacturability/Yield and Statistical Design
* Puneet Gupta (UC Los Angeles, USA)
Toshiyuki Shibuya (Fujitsu Laboratories, Japan)
Murakata Masami (STARC, Japan)
Kartik Mohanram (Rice Univ., USA)
Andrew B. Kahng (UC San Diego, USA)
Fedor G. Pikus (Mentor Graphics, USA)
Zheng Shi (Zhejiang Univ., China)
[11] Test and Design for Testability
* Seiji Kajihara (Kyusyu Institute of Technology, Japan)
Tomokazu Yoneda (NAIST, Japan)
Shi-Yu Huang (National Tsing-Hua Univ., Taiwan)
Kee Sup Kim (Samsung, Korea)
Sungho Kang (Yonsei Univ., Korea)
Yu Huang (Mentor Graphics, USA)
[12] Analog, RF and Mixed Signal Design and CAD
* Jaijeet Roychowdhury (UC Berkeley, USA)
Eric Keiter (Sandia National Labs, USA)
Chin-Fong Chiu (National Chip Implementation Center, Taiwan)
Hao Yu (Nanyang Technological Univ., Singapore)
[13] Emerging Technologies and Applications
* Chin-Long Wey (National Central Univ., Taiwan)
In-Cheol Park ( KAIST, Korea)
Mehdi Baradaran Tahoori (Northeastern Univ., USA)
Chun-Ming Huang (National Chip Implementation Center, Taiwan)
Xiaoyang Zeng (Fudan Univ., China)
Wei Zhang (Nanyang Technological Univ., Singapore)
Hai (Helen) Li (Polytechnic Institute of New York Univ., USA)
Jin-Fu Li (National Central Univ., Taiwan)
Chi-Sheng Li (National Chip Implementation Center, Taiwan)

Last Updated on: 6 7, 2010