Tutorials

ASP-DAC 2021 offers attendees a set of three-hour intense introductions to specific topics. This year, each tutorial will be provided interactive online plus recorded videos.

  • Date: Monday, January 18, 2021 (9:00 — 17:00)
Room 1 Room 2 Room 3
9:00 — 12:00 (JST) Tutorial-1
Achieving quantum computing's disruptive capabilities through error-mitigating software		 Tutorial-2
Reliability and availability of hardware-software systems — Stochastic Reliability Models of Real Systems		 Tutorial-3
Machine Learning in EDA Tutorial: Approaches, Advantages, Challenges and Examples
14:00 — 17:00 (JST) Tutorial-4
The latest Heterogenous Integration Packaging trends for 5G, Artificial Intelligence, Automotive Electronics, and High Performance Computing		 Tutorial-5
Emerging Devices from Manufacturing Point of View: 3D NAND Flash Memory, PCRAM and Carbon Nanotube

Tutorial-1: Monday, January 18, 9:00—12:00 (JST) @ Room 1

Achieving quantum computing's disruptive capabilities through error-mitigating software

Speaker:
Joseph Emerson (Quantum Benchmark Inc. / University of Waterloo)

Abstract:

Quantum computers will achieve disruptive capabilities only if they can overcome their intrinsic sensitivity to quantum error sources. These error sources, if unmitigated, lead to inaccurate and incorrect quantum computing solutions. I will describe the current status of quantum computing capabilities, key challenges, and the roadmap to achieving quantum advantage in the future. I will present some of our state-of-the-art results from current generation quantum computing platforms that leverage Quantum Benchmark's error-mitigating software solutions.

Biography:

Joseph Emerson is CEO and Chief Scientist at Quantum Benchmark Inc and a Professor of Applied Math at the Institute for Quantum Computing at the University of Waterloo. He developed the now industry-standard techniques that advance the quantum computing capabilities through identifying and suppressing quantum error sources.



Tutorial-2: Monday, January 18, 9:00—12:00 @ Room 2

Reliability and availability of hardware-software systems — Stochastic Reliability Models of Real Systems

Speaker:
Kishor S. Trivedi (Duke University)

Abstract:

High reliability and availability are requirements for most technical systems including computer and communication systems. Reliability and availability assurance methods based on probabilistic models is the topic addressed in this talk. Non-state-space solution methods are often used to solve models based on reliability block diagrams, fault trees and reliability graphs. Relatively efficient algorithms are known to handle systems with hundreds of components and have been implemented in many software packages. Nevertheless, many practical problems cannot be handled by such algorithms. Bounding algorithms are then used in such cases as was done for a major subsystem of Boeing 787. Non-state-space methods derive their efficiency from the independence assumption that is often violated in practice. State space methods based on Markov chains, stochastic Petri nets, semi-Markov and Markov regenerative processes can be used to model various kinds of dependencies among system components. Linux Operating System and WebSphere Application server are used as examples of Markov models. IBM research cloud is used as an example of stochastic Petri net model. However, the state space explosion of such models severely restricts the size of the problem that can be solved. Hierarchical and fixed-point iterative methods provide a scalable alternative that combines the strengths of state space and non-state-space methods and have been extensively used to solve real-life problems. Real-world examples of such multi-level models from IBM, Cisco and Sun Microsystems will be discussed. Hardware systems as well as software systems and their combinations will be addressed via these examples. Novel approaches to software fault tolerance will be discussed. These methods and applications are fully described in a recently completed book: Reliability and Availability Engineering: Modeling, Analysis and Applications, Cambridge University Press, 2017.

Biography:

Kishor Trivedi holds the Fitzgerald Hudson Chair in the Department of Electrical and Computer Engineering at Duke University, Durham, NC. He has a 1968 B.Tech. (EE) from IIT Mumbai and MS’72/PhD’74 (CS) from the University of Illinois at Urbana-Champaign. He has been on the Duke faculty since 1975. He is the author of a well-known text entitled, Probability and Statistics with Reliability, Queuing and Computer Science Applications, originally published by Prentice-Hall; a thoroughly revised second edition of this book has been published by John Wiley. The book is recently translated into Chinese. He has also published two other books entitled, Performance and Reliability Analysis of Computer Systems, published by Kluwer Academic Publishers and Queueing Networks and Markov Chains, John Wiley. His latest book, Reliability and Availability Engineering is published by Cambridge University Press in 2017. He is a Life Fellow of the Institute of Electrical and Electronics Engineers and a Golden Core Member of IEEE Computer Society. He has published over 600 articles and has supervised 48 Ph.D. dissertations. He is the recipient of IEEE Computer Society’s Technical Achievement Award for his research on Software Aging and Rejuvenation. He is the recipient of IEEE Reliability Society’s Life Time Achievement Award. His h-index is 104. He has worked closely with industry in carrying our reliability/availability analysis, providing short courses on reliability, availability, and in the development and dissemination of software packages such as HARP, SHARPE, SREPT and SPNP.

Tutorial-3: Monday, January 18, 9:00—12:00 @ Room 3

Machine Learning in EDA Tutorial: Approaches, Advantages, Challenges and Examples

Speaker:
Elias Fallon (Cadence Design Systems, Inc.)

Abstract:

Electronic Design Automation (EDA) software has delivered semiconductor design productivity improvements for decades. The next leap in productivity will come from the addition of machine learning (ML) techniques to the toolbox of computational software capabilities employed by EDA developers. Recent research and development into machine learning for EDA point to clear patterns for how it impacts EDA tools, flows, and design challenges. This research has also illustrated some of the challenges that will come with production deployment of machine learning techniques into EDA tools and flows. This tutorial will detail patterns observed in ML for EDA development. The advantages and disadvantages of different ML approaches as well as the challenges for deployment in EDA developments will be discussed. Specific examples of different ML approaches in the EDA domain will be presented, and the opportunities and open questions for future research will be shown.

Biography:

Elias Fallon is currently Engineering Group Director at Cadence Design Systems, a leading Electronic Design Automation company. He has been involved in EDA for more than 20 years from the founding of Neolinear, Inc, which was acquired by Cadence in 2004. Elias was co-Primary Investigator on the MAGESTIC project, funded by DARPA to investigate the application of Machine Learning to EDA for Package/PCB and Analog IC. Elias also leads an innovation incubation team within the Custom IC R&D group as well as other traditional EDA product teams. Beyond his work developing electronic design automation tools, he has led software quality improvement initiatives within Cadence, partnering with the Carnegie Mellon Software Engineering Institute. Elias graduated from Carnegie Mellon University with an M.S. and B.S. in Electrical and Computer Engineering. Elias, his wife and two children live north of Pittsburgh, PA, USA. https://www.linkedin.com/in/elias-fallon/

Tutorial-4: Monday, January 18, 14:00—17:00 @ Room 1

The latest Heterogenous Integration Packaging trends for 5G, Artificial Intelligence, Automotive Electronics, and High Performance Computing

Speaker:
Henry H. Utsunomiya (Interconnection Technologies, Inc.)

Abstract:

Heterogeneous Integration refers to the assembly and packaging of multiple separately manufactured components in order to improve functionality and enhance operating characteristics. And it allows for the packaging of components of different functionalities, different process technologies, different materials and sometimes separate manufacturers.

Since Moore’s Law scaling pace has been slowing down, increasing functionality of monolithic die on the same area and/or same footprint by System on Chip (SoC) without increasing cost per transistors becoming difficult. Heterogenous Integration technology building blocks such as 3D integration, Chiplets, and embedded dies into packaging substrate implementation into System-in-Package (SiP) provides alternative solutions to both microelectronics industry and electronics systems with shorter time to market and affordable cost.

In this tutorial, introduce current status of Heterogeneous Integration technology, its building blocks, use case examples e.g. 5th Generation Mobile Communication (5G), Ambient Assisted Living, Artificial Intelligence (AI), Autonomous Driving, Industry 4.0, Health Care, Internet of Things (IoT), supply chain and roadmap toward 2030 will be discussed.

Biography:

Henry H. Utsunomiya (Interconnection Technologies, Inc.)
  • President of Interconnection Technologies, Inc.
  • A METI registered small and medium enterprise business consultant
  • Chairman of JPCA Technology Roadmap of PWBs
  • Co-Chairman of Organic Substrate Technology Roadmap, iNEMI
  • A member of the Jisso Technology Roadmap committee, JIETA
  • A recipient of the IPC President’s Award


Tutorial-5: Monday, January 18, 14:00—17:00 @ Room 2

Emerging Devices from Manufacturing Point of View: 3D NAND Flash Memory, PCRAM and Carbon Nanotube

Speakers:
Koukou Suu (Ulvac Technologies, Inc.)
Yoshihiro Hirota (Tokyo Electron Limited)
Shigemi Murakawa (Zeon Corporation)

Abstract:

This tutorial covers three topics:

1. Manufacturing Technology of Phase Change Memory for Storage Class Memory and AI Applications
Koukou Suu (Ulvac Technologies, Inc.)
Thin-film functional material such as phase-change (Ge2Sb2Te5) and selector materials have been utilizing to form advanced semiconductor devices including Phase-Change Random Access Memory (PCRAM) for Storage Class memory (Ge-As-Se) and analog Artificial Intelligence (AI). In this talk, we will give presentation our development activities of phase-change material thin- film processing technologies including sputtering, ALD/CVD as well as manufacturing processes for Phase-Change Random Access Memory (PCRAM).

2. 3D NAND Flash Memory, Manufacturing Technology and Trend
Yoshihiro Hirota (Tokyo Electron Limited)
NAND Flash memory was invented in 1980s and the first paper in the world was published in IEDM 1987 by F. Masuoka Group, Toshiba. The bit density has been increased by the scaling technology of manufacturing process, and the structure has been changed from 2D to 3D structure to increase the bit density. Recently, 3D NAND with 128 WLs has been developed and shipped, and the bit density has been achieved to 7.8Gbit/mm2. A general manufacturing process flow of 3D NAND and some key processes are introduced. The aggressive manufacturing process technologies are visually shown. High aspect ratio etching process technology is highly aggressive to fabricate the memory cell holes. The aspect ratio becomes more than 45 now. The conformal thin film deposition technology into the memory cell holes with vertical structure is also highly aggressive.
Vertical scaling, horizontal scaling and electrical scaling are challenging to increase the bit density today. In vertical scaling, there are stack layer increase, shrink of each layer thickness and others. In horizontal scaling, there are the scaling of the memory cell hole layout, an introduction of Circuit (or CMOS) under Array (CuA) structure and other new structures. Finally, electrical scaling challenge is multi bit cell technology. There are Floating Gate type and Charge Trap Film type in 3D NAND. The advantages and disadvantages of both type NANDs are also discussed.

3. Carbon nanotube and its Electronic Device Applications
Shigemi Murakawa (Zeon Corporation)
This tutorial reviews the manufacturing method of the single-walled carbon nanotube and its advantageous characteristics such as extremely low impurities, high specific surface area and high electric conductivity. Also described are its various device applications including non-volatile memory, high-density capacitor, electric elastomer, microwave-shielding film and the thermo-electric conversion device. Here, the adaptive design and operation of the device are important, considering the process and material-characteristics windows. Also, the AI-based QC system which covers from the material characteristics to the device performance is highly expected.

Biography:

KOUKOU SUU, PhD
Executive Officer and Senior Fellow at ULVAC, Inc.
President and CEO at ULVAC Technologies, Inc.
TERTIARY EDUCATION
PhD, Tohoku University, Japan 1993.
MSc, Tohoku University, Japan 1988.
CAREER EXPERIENCE
Employment:
Dr.Koukou Suu is Executive Officer and Senior Fellow of ULVAC, and also President and CEO of ULVAC Technologies Inc since 2019. He was the General Manager of Global Market and Technology Strategy Division from 2014 to 2019. Prior to this, He served as the General Manager of Institute of Semiconductor and Electronics Technologies from 2008 to 2014. At Institute of Semiconductor and Electronics Technologies, he worked on Ferroelectric MEMS Technologies, emerging non-volatile memories, high-K capacitors, LED, power devices, thinfilm Li-battery as well as 3D packaging manufacturing technologies.
Expertise:
Ferroelectric MEMS Technology Development for the Mass Production of the Sensor.
Heterogeneous Integration Technology Development
Technology Development for the Mass Production of PCRAM (by Sputtering and MOCVD etc.)
Technology Development for the Mass Production of FeRAM (by Sputtering, MOCVD, Plasma Etching and Ashing etc.)
Technology Development for the Mass Production of ReRAM
Technology Development of High Permittivity Thin Film Used on the High-Volume Capacitor for the Mass
Production of the Next Generation DRAM
Research Development for the Thin Film Li-ion Battery.
LED Mass Production Technology Development

Yoshihiro Hirota is now working for Tokyo Electron Ltd. He graduated and received a master’s degree from Kyoto Institute of Technology at 1987. After the graduating from the university, he had jointed to Sanyo Electric Co., Ltd. at 1987. He had worked for Advance Technology Research Laboratories, Sumitomo Metal Industries, Ltd. from 1991 to 2000. He had worked for Innotech Corporation from 2000 to 2001. At 2001, he had joined to Tokyo Electron Ltd., and been a group manager of FEOL process development. He is now in charge of Project Leader of Memory Technology Project, Device Technology Planning Dept., Corporate Innovation Div. in Tokyo Electron Ltd.

Shigemi Murakawa is now working for ZEON corporation since 2013, focusing the carbon nanotube devices. Before joining ZEON, he worked for Kawasaki Steel (now JFE Steel) in 1982 – 1997, Tokyo Electron in 1997 - 2007, Varian Semiconductor Equipment (now Applied Materials) in 2007 - 2012. He also stayed at Stanford University in 1991 – 1993 as a visiting scholar for researching the surface charge-up of the semiconductor devices and its effect to the device degradation during the plasma processing.
Last Updated on: November 29, 2020