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Session 1B: Power and Thermal Modeling and Optimization
1B-1 (Time: 10:15 - 10:40)
| Title |
Predictive Power Aware Management for Embedded Mobile Devices |
| Author |
*Young-Si Hwang, Sung-Kwan Ku, Chan-Min Jung, Ki-Seok Chung (Hanyang Univ., Korea) |
| Abstract |
Intelligent power management of mobile devices is getting more important as ubiquitous computing is coming true in daily life. Power aware system management relies on techniques of collecting and analyzing information on the status of I/O devices or processors while some application is running. However, the overhead of collecting information using SW while the system is running is so huge that performance of the system may be severely deteriorated. Therefore, it is very crucial to design a PMU (power management unit) which collects information in HW so that the performance of the system is not degraded. In this paper, we propose a novel PMU design which collects information of I/O device while an application is running, and the power aware management is carried out based on the collected information. Experiments with various applications have been conducted to show the effectiveness of our design. |
| No Slides |
1B-2 (Time: 10:40 - 11:05)
| Title |
A Dynamic-Programming Algorithm for Reducing the Energy Consumption of Pipelined System-Level Streaming Applications |
| Author |
N. Liveris, *H. Zhou (Northwestern Univ., USA), P. Banerjee (HP Labs, USA) |
| Abstract |
In this paper we present a System-Level technique for reducing energy consumption. The technique is applicable to pipelined applications represented as chain-structured graphs and targets the energy overhead of switching between active and sleep mode. The overhead is reduced by increasing the number of consecutive executions of the pipeline stages. The technique has no impact on the average throughput. We derive upper bounds on the number of consecutive executions and present a dynamic-programming algorithm that finds the optimal solution using these bounds. For specific cases we derive a quality metric that can be used to trade quality of the result for running-time. |
| Slides |
1B-3 (Time: 11:05 - 11:30)
| Title |
Temperature-Aware MPSoC Scheduling for Reducing Hot Spots and Gradients |
| Author |
*Ayse Kivilcim Coskun, Tajana Simunic Rosing (Univ. of California, San Diego, USA), Keith A. Whisnant, Kenny C. Gross (Sun Microsystems, USA) |
| Abstract |
Thermal hot spots and temperature gradients on the die need to be minimized to manufacture reliable systems while meeting energy and performance constraints. In this work, we solve the task scheduling problem for multiprocessor system-on-chips (MPSoCs) using Integer Linear Programming (ILP). The goal of our optimization is minimizing the hot spots and balancing the temperature distribution on the die for a known set of tasks. Under the given assumptions about task characteristics, the solution is optimal. We compare our technique against optimal scheduling methods for energy minimization, energy balancing, and hot spot minimization, and show that our technique achieves significantly better thermal profiles. We also extend our technique to handle workload variations at runtime. |
| No Slides |
1B-4 (Time: 11:30 - 11:55)
| Title |
Run-Time Power Gating of On-Chip Routers Using Look-Ahead Routing |
| Author |
*Hiroki Matsutani (Keio Univ., Japan), Michihiro Koibuchi (National Institute of Informatics, Japan), Daihan Wang, Hideharu Amano (Keio Univ., Japan) |
| Abstract |
Since on-chip routers in Network-on-Chips play a key role for enabling on-chip communication between cores, they must be always preparing for packet injections even if a part of cores are in standby mode, resulting in a larger standby power of routers compared with cores. The run-time power gating of individual channels in a router is one of attractive solutions to reduce the standby power of chip without affecting the on-chip communication. However, a state transition between sleep and active mode incurs the performance penalty, and turning a power switch on or off dissipates the overhead energy, which means a short-term sleep adversely increases the power consumption. In this paper, we propose a sleep control method based on look-ahead routing that detects the arrival of packets two hops ahead, so as to hide the wake-up delay and reduce the short-term sleeps of channels. Simulation results using real application traces show that the proposed method conceals the wake-up delay of less than five cycles, and more leakage power can be saved compared with the original naive method. |
| No Slides |
1B-5 (Time: 11:55 - 12:08)
| Title |
Automated Techniques for Energy Efficient Scheduling on Homogeneous and Heterogeneous Chip Multi-Processor Architectures |
| Author |
*Sushu Zhang, Karam S. Chatha (Arizona State Univ., USA) |
| Abstract |
We address performance maximization of independent task sets under energy constraint on chip multi-processor (CMP) architectures that support multiple voltage/frequency operating states for each core. We prove that the problem is strongly NP-hard. We propose polynomial time 2-approximation algorithms for homogeneous and heterogeneous CMPs. To the best of our knowledge, our techniques offer the tightest bounds for energy constrained design on CMP architectures. Experimental results demonstrate that our techniques are effective and efficient under various workloads on several CMP architectures. |
| No Slides |
1B-6 (Time: 12:08 - 12:21)
| Title |
Statistical Power Profile Correlation for Realistic Thermal Estimation |
| Author |
*Love Singhal (Univ. of California, Irvine, USA), Sejong Oh (KAIST, Korea), Eli Bozorgzadeh (Univ. of California, Irvine, USA) |
| Abstract |
At system level, the on-chip temperature depends both on power density and the thermal coupling with the neighboring region. The problem of finding the right set of input power profile(s) for accurate temperature estimation has not been studied. Considering only average or peak power density may lead either to underestimation or overestimation of the thermal crisis, respectively. To provide more realistic temperature estimation, we propose to incorporate multiple power profile representation, referred to as leader power profiles. Using the proposed statistical methods to determine the closeness between the power profiles, we apply a clustering algorithm to identify leader power profiles. We incorporate them in a thermal-aware floorplanner and empirical results show that using the single leader power profile (average or peak) leads to 37% degradation in critical wire delay and 20% degradation in wire length, compared to using the multiple leader power profiles. |
| Slides |
Last Updated on: January 31, 2008
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