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Session 8A: Test Generation and Test Power
8A-1 (Time: 13:30 - 13:55)
| Title |
Circuit Lines for Guiding the Generation of Random Test Sequences for Synchronous Sequential Circuits |
| Author |
Irith Pomeranz (Purdue Univ., USA), *Sudhakar M. Reddy (Univ. of Iowa, USA) |
| Abstract |
A procedure proposed earlier for improving the fault coverage of a random primary input sequence modifies the input sequence so as to avoid repeated synchronization of state variables. We show that in addition to the values of state variables, it is also important to consider repeated setting of other lines to the same values. A procedure and experimental results are presented to demonstrate the improvements in fault coverage of random primary input sequences when the values of selected lines are considered. |
| Slides |
8A-2 (Time: 13:55 - 14:20)
| Title |
A New Low Energy BIST Using A Statistical Code |
| Author |
*Sunghoon Chun, Taejin Kim, Sungho Kang (Yonsei Univ., Korea) |
| Abstract |
To tackle with the increased switching activity during the test operation, this paper proposes a new built-in self test (BIST) scheme for low energy testing that uses a statistical code and a new technique to skip unnecessary test sequences. From a general point of view, the goal of this technique is to minimize the total power consumption during a test and to allow the at-speed test in order to achieve high fault coverage. The effectiveness of the proposed low energy BIST scheme was validated on a set of ISCAS ’89 benchmark circuits with respect to test data volume and energy saving. |
| Slides |
8A-3 (Time: 14:20 - 14:33)
| Title |
On Reducing Both Shift and Capture Power for Scan-Based Testing |
| Author |
Jia Li (Chinese Academy of Sciences, China), *Qiang Xu (The Chinese Univ. of Hong Kong, Hong Kong), Yu Hu, Xiaowei Li (Chinese Academy of Sciences, China) |
| Abstract |
Power consumption in scan-based testing is a major concern nowadays. In this paper, we present a new X-filling technique to reduce both shift power and capture power during scan tests, namely LSC-filling. The basic idea is to use as few as possible X-bits to keep the capture power under the peak power limit of the circuit under test (CUT), while using the remaining X-bits to reduce the shift power to cut down the CUT’s average power consumption during scan tests as much as possible. In addition, by carefully selecting the X-filling order, our X-filling technique is able to achieve lower capture power when compared to existing methods. Experimental results on ISCAS’89 benchmark circuits show the effectiveness of the proposed methodology. |
| Slides |
8A-4 (Time: 14:33 - 14:46)
| Title |
Robust Test Generation for Power Supply Noise Induced Path Delay Faults |
| Author |
*Xiang Fu, Huawei Li, Yu Hu, Xiaowei Li (Chinese Academy of Sciences, China) |
| Abstract |
In deep sub-micron designs, the delay caused by power supply noise (PSN) can no longer be ignored. A PSN-induced path delay fault (PSNPDF) model is proposed in this paper, and should be tested to enhance chip quality. Based on precise timing analysis, we also propose a robust test generation technique for PSNPDF. Concept of timing window is introduced into the PSNPDF model. If two devices in the same feed region simultaneously switch in the same direction, the current waveform of the two devices will have an overlap and excessive PSN will be produced. Experimental results on ISCAS’89 circuits showed test generation can be finished in a few seconds. |
| Slides |
8A-5 (Time: 14:46 - 14:59)
| Title |
Test Vector Chains for Increased Targeted and Untargeted Fault Coverage |
| Author |
Irith Pomeranz (Purdue Univ., USA), *Sudhakar M. Reddy (Univ. of Iowa, USA) |
| Abstract |
We introduce the concept of test vector chains, which allows us to obtain new test vectors from existing ones through single-bit changes without any test generation effort. We demonstrate that a test set T0 has a significant number of test vector chains that are effective in increasing the numbers of detections of target faults, i.e., faults targeted during the generation of T0, as well as untargeted faults, i.e., faults that were not targeted during the generation of T0. |
| Slides |
8A-6 (Time: 14:59 - 15:12)
| Title |
Parallel Fault Backtracing for Calculation of Fault Coverage |
| Author |
*Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman (Tallinn Univ. of Tech., Estonia) |
| Abstract |
An improved method for calculation of fault coverage with parallel fault backtracing in digital circuits with scan path is proposed. The method is based on structurally synthesized BDDs (SSBDD) which represent gate-level circuits at higher, macro level where macros represent subnetworks of gates. A topological analysis is carried out to generate an efficient model for backtracing of faults to minimize the repeated calculations because of the reconvergent fanouts. The algorithm is equivalent to exact critical path tracing. Because of the parallelism and higher abstraction level modeling the speed of analysis was considerably increased. Experimental data show that the speed-up of the new method is considerable compared to the previous similar approach. The speed of the fault analysis in several times outperforms the speed of the current state-of-the-art commercial fault simulators |
| Slides |
Last Updated on: January 31, 2008
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