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The 13th Asia and South Pacific Design Automation Conference
Technical Program

Remark: The presenter of each paper is marked with "*".
Technical Program:   SIMPLE version   DETAILED version with abstract    One Page (Not Separated) version
Author Index:   HERE

Session Schedule


Tuesday, January 22, 2008

ABCD
Op (Room 409)
Opening Ceremony
08:30 - 09:00
1K (Room 409)
Keynote Session I
09:00 - 10:00
Coffee Break
10:00 - 10:15
1A (Room 310A)
New Challenges in High Level Synthesis
10:15 - 12:20
1B (Room 310BC)
Power and Thermal Modeling and Optimization
10:15 - 12:20
1C (Room 311A)
Emerging Technologies
10:15 - 12:20
1D (Room 311BC)
University LSI Design Contest
10:15 - 12:20
Lunch
12:20 - 13:30
2A (Room 310A)
Advanced Topic in Logic Synthesis
13:30 - 15:35
2B (Room 310BC)
Interconnect Modeling and Simulation Techniques
13:30 - 15:35
2C (Room 311A)
Floorplanning
13:30 - 15:35
2D (Room 311BC)
Special Session - Tackling Manufacturability/Variability for 32nm and Below
13:30 - 15:35
Coffee Break
15:35 - 15:50
3A (Room 310A)
Routing
15:50 - 17:55
3B (Room 310BC)
Interconnect, NoCs, and MPSoCs
15:50 - 17:30
3D (Room 311A+311BC)
Special Session (Panel) The Tears and Joy of Sowing and Reaping Complex SoC's
15:50 - 17:55


Wednesday, January 23, 2008

ABCD
2K (Room 409)
Keynote Session II
9:00 - 10:00
Coffee Break
10:00 - 10:15
4A (Room 310A)
Variability Issues in Timing
10:15 - 12:20
4B (Room 310BC)
Memory and Processor Optimization
10:15 - 12:20
4C (Room 311A)
New Techniques for Physical Design Optimization
10:15 - 12:20
4D (Room 311BC)
Designers' Forum - New Emerging Application Areas for Future SoC
10:15 - 12:20
Lunch
12:20 - 13:30
5A (Room 310A)
Techniques for Formal and Simulation-Based Varification
13:30 - 15:35
5B (Room 310BC)
Power and Performance Optimization for Embedded Systems
13:30 - 15:35
5C (Room 311A)
Thermal Analysis and DFM
13:30 - 15:35
5D (Room 311BC)
Designers' Forum (Panel) Are System Level EDA Tools/Methodologies Coming?
13:30 - 15:35
Coffee Break
15:35 - 15:50
6A (Room 310A)
Trends in Timing
15:50 - 17:55
6B (Room 310BC)
Statistical Modeling and Yield Prediction
15:50 - 17:55
6D (Room 311A+311BC)
Special Session - How to Design Cool Chips for Hot Products
15:50 - 17:55


Thursday, January 24, 2008

ABCD
3K (Room 409)
Keynote Session III
9:00 - 10:00
Coffee Break
10:00 - 10:15
7A (Room 310A)
Reliable/Testable Design Techniques
10:15 - 12:20
7B (Room 310BC)
Communication and Interfaces
10:15 - 12:20
7C (Room 311A)
Power: Delivery and Reduction
10:15 - 12:20
7D (Room 311BC)
Special Session (Panel) Concurrent SoC and SiP Designs
10:15 - 12:20
Lunch
12:20 - 13:30
8A (Room 310A)
Test Generation and Test Power
13:30 - 15:35
8B (Room 310BC)
Design Space Exploration
13:30 - 15:35
8C (Room 311A)
Reliability and Power Management
13:30 - 15:35
8D (Room 311BC)
Designers' Forum - Low Power Chips
13:30 - 15:35
Coffee Break
15:35 - 15:50
9A (Room 310A)
Analog/RF/Mixed Signal CAD
15:50 - 17:55
9B (Room 310BC)
Architecture Exploration
15:50 - 17:55
9D (Room 311BC)
Designers' Forum (Panel) Best Ways to Use Billions of Devices on a Chip
15:50 - 17:55