| Title | A 40-nm 144-mW VLSI Processor for Real-time 60-kWord Continuous Speech Recognition |
| Author | *Guangji He, Takanobu Sugahara, Tsuyoshi Fujinaga, Yuki Miyamoto, Hiroki Noguchi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ., Japan) |
| Page | pp. 71 - 72 |
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| Title | A 24.5-53.6pJ/pixel 4320p 60fps H.264/AVC Intra-Frame Video Encoder Chip in 65nm CMOS |
| Author | *Dajiang Zhou, Gang He, Wei Fei, Zhixiang Chen, Jinjia Zhou, Satoshi Goto (Waseda Univ., Japan) |
| Page | pp. 73 - 74 |
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| Title | A Low Power Multimedia Processor Implementing Dynamic Voltage and Frequency Scaling Technique |
| Author | Tadayoshi Enomoto, *Nobuaki Kobayashi (Chuo Univ., Japan) |
| Page | pp. 75 - 76 |
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| Title | A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Power Disturb Mitigation Technique |
| Author | *Shusuke Yoshimoto, Masaharu Terada, Shunsuke Okumura (Kobe Univ., Japan), Toshikazu Suzuki (Panasonic Corp., Japan), Shinji Miyano (STARC, Japan), Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ., Japan) |
| Page | pp. 77 - 78 |
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| Title | A Physical Unclonable Function Chip Exploiting Load Transistors’ Variation in SRAM Bitcells |
| Author | *Shunsuke Okumura, Shusuke Yoshimoto, Hiroshi Kawaguchi (Kobe Univ., Japan), Masahiko Yoshimoto (Kobe Univ./JST CREST, Japan) |
| Page | pp. 79 - 80 |
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| Title | Over 10-Times High-speed, Energy Efficient 3D TSV-Integrated Hybrid ReRAM/MLC NAND SSD by Intelligent Data Fragmentation Suppression |
| Author | *Chao Sun (Chuo Univ./Univ. of Tokyo, Japan), Hiroki Fujii (Univ. of Tokyo, Japan), Kousuke Miyaji, Koh Johguchi (Chuo Univ., Japan), Kazuhide Higuchi (Univ. of Tokyo, Japan), Ken Takeuchi (Chuo Univ., Japan) |
| Page | pp. 81 - 82 |
| Detailed information (abstract, keywords, etc) | |
| Title | Highly Reliable Solid-State Drives (SSDs) with Error-Prediction LDPC (EP-LDPC) Architecture and Error-Recovery Scheme |
| Author | *Shuhei Tanakamaru, Yuki Yanagihara (Univ. of Tokyo, Japan), Ken Takeuchi (Chuo Univ., Japan) |
| Page | pp. 83 - 84 |
| Detailed information (abstract, keywords, etc) | |
| Title | A 3Gb/s 2.08mm2 100b Error-Correcting BCH Decoder in 0.13µm CMOS Process |
| Author | *Youngjoo Lee, Hoyoung Yoo, In-Cheol Park (KAIST, Republic of Korea) |
| Page | pp. 85 - 86 |
| Detailed information (abstract, keywords, etc) | |
| Title | A 6.72-Gb/s, 8pJ/bit/iteration WPAN LDPC Decoder in 65nm CMOS |
| Author | *Zhixiang Chen, Xiao Peng, Xiongxin Zhao, Leona Okamura, Dajiang Zhou, Satoshi Goto (Waseda Univ., Japan) |
| Page | pp. 87 - 88 |
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| Title | A 7.5Gb/s Referenceless Transceiver for UHDTV with Adaptive Equalization and Bandwidth Scanning Technique in 0.13um CMOS Process |
| Author | *Junyoung Song (Korea Univ., Republic of Korea), Hyunwoo Lee (Hynix Inc., Republic of Korea), Sewook Hwang (Korea Univ., Republic of Korea), Inhwa Jung (Hynix Inc., Republic of Korea), Chulwoo Kim (Korea Univ., Republic of Korea) |
| Page | pp. 89 - 90 |
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| Title | A 12.5 Gb/s/Link Non-Contact Multi Drop Bus System with Impedance-Matched Transmission Line Couplers and Dicode Partial-Response Channel Transceivers |
| Author | *Atsutake Kosuge, Wataru Mizuhara, Noriyuki Miura, Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda (Keio Univ., Japan) |
| Page | pp. 91 - 92 |
| Detailed information (abstract, keywords, etc) | |
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| Title | 315MHz OOK Transceiver with 38-µW Receiver and 36-µW Transmitter in 40-nm CMOS |
| Author | *Shunta Iguchi (Univ. of Tokyo, Japan), Akira Saito (STARC, Japan), Kentaro Honda, Yunfei Zheng (Univ. of Tokyo, Japan), Kazunori Watanabe (STARC, Japan), Takayasu Sakurai, Makoto Takamiya (Univ. of Tokyo, Japan) |
| Page | pp. 93 - 94 |
| Detailed information (abstract, keywords, etc) | |
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| Title | A Full 4-Channel 60GHz Direct-Conversion Transceiver |
| Author | *Seitaro Kawai, Ryo Minami, Ahmed Musa, Takahiro Sato, Ning Li, Tatsuya Yamaguchi, Yasuaki Takeuchi, Yuki Tsukui, Kenichi Okada, Akira Matsuzawa (Tokyo Inst. of Tech., Japan) |
| Page | pp. 95 - 96 |
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| Title | A Sub-harmonic Injection-locked Frequency Synthesizer with Frequency Calibration Scheme for Use in 60GHz TDD Transceivers |
| Author | *Teerachot Siriburanon, Wei Deng, Ahmed Musa, Kenichi Okada, Akira Matsuzawa (Tokyo Inst. of Tech., Japan) |
| Page | pp. 97 - 98 |
| Detailed information (abstract, keywords, etc) | |
| Title | A Fractional-N Harmonic Injection-locked Frequency Synthesizer with 10MHz-6.6GHz Quadrature Outputs for Software-Defined Radios |
| Author | *Wei Deng, Ahmed Musa, Kenichi Okada, Akira Matsuzawa (Tokyo Inst. of Tech., Japan) |
| Page | pp. 99 - 100 |
| Detailed information (abstract, keywords, etc) | |
| Title | A Ring-VCO-Based Sub-Sampling PLL CMOS Circuit with 0.73 ps Jitter and 20.4 mW Power Consumption |
| Author | *Kenta Sogo, Akihiro Toya, Takamaro Kikkawa (Hiroshima Univ., Japan) |
| Page | pp. 101 - 102 |
| Detailed information (abstract, keywords, etc) | |
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| Title | Design of a Clock Jitter Reduction Circuit Using Gated Phase Blending Between Self-Delayed Clock Edges |
| Author | *Kiichi Niitsu, Naohiro Harigai, Daiki Hirabayashi, Daiki Oki, Masato Sakurai (Gunma Univ., Japan), Osamu Kobayashi (STARC, Japan), Takahiro J. Yamaguchi, Haruo Kobayashi (Gunma Univ., Japan) |
| Page | pp. 103 - 104 |
| Detailed information (abstract, keywords, etc) | |
| Title | A 25-Gb/s LD Driver with Area-Effective Inductor in a 0.18-µm CMOS |
| Author | *Takeshi Kuboki (Kyoto Univ., Japan), Yusuke Ohtomo (NTT, Japan), Akira Tsuchiya (Kyoto Univ., Japan), Keiji Kishine (Univ. of Shiga Prefecture, Japan), Hidetoshi Onodera (Kyoto Univ., Japan) |
| Page | pp. 105 - 106 |
| Detailed information (abstract, keywords, etc) | |
| Slides | |
| Title | A Regulated Charge Pump with Low-Power Integrated Optimum Power Point Tracking Algorithm for Indoor Solar Energy Harvesting |
| Author | *Jungmoon Kim, Chulwoo Kim (Korea Univ., Republic of Korea) |
| Page | pp. 107 - 108 |
| Detailed information (abstract, keywords, etc) | |
| Slides | |
| Title | A Low Voltage Buck DC-DC Converter Using On-Chip Gate Boost Technique in 40nm CMOS |
| Author | *Xin Zhang, Po-Hung Chen (Univ. of Tokyo, Japan), Yoshikatsu Ryu (STARC, Japan), Koichi Ishida (Univ. of Tokyo, Japan), Yasuyuki Okuma, Kazunori Watanabe (STARC, Japan), Takayasu Sakurai, Makoto Takamiya (Univ. of Tokyo, Japan) |
| Page | pp. 109 - 110 |
| Detailed information (abstract, keywords, etc) | |
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| Title | A 0.35-0.8V 8b 0.5-35MS/s 2bit/step Extremely-low Power SAR ADC |
| Author | *Kentaro Yoshioka, Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro (Keio Univ., Japan) |
| Page | pp. 111 - 112 |
| Detailed information (abstract, keywords, etc) | |
| Slides | |