Session 6A: Trends in Timing

6A-1 (Time: 15:50 - 16:15)

Title Pessimism Reduction in Coupling-Aware Static Timing Analysis Using Timing and Logic Filtering
Author *Debasish Das (Northwestern Univ., USA), Kip Killpack, Chandramouli Kashyap, Abhijit Jas (Intel, USA), Hai Zhou (Northwestern Univ., USA)
Abstract With continued scaling of technology into nanometer regimes, the impact of coupling induced delay variations are significant. While several coupling aware static timers have been proposed, the results are often pessimistic with many false failures. We present an integrated iterative timing filtering and logic filtering based approach to reduce pessimism. We use a realistic coupling model based on arrival times and slews and show that non-iterative pessimism reduction algorithms proposed by previous research can give potentially non-conservative timing results. On a functional block from an industrial 65nm microprocessor our algorithm showed a maximum pessimism reduction of 11.18\% of cycle time over converged timing filtering analysis that does not consider logic constraints.

6A-2 (Time: 16:15 - 16:40)

Title A Fast Incremental Clock Skew Scheduling Algorithm for Slack Optimization
Author *Kui Wang, Hao Fang, Hu Xu, Xu Cheng (Microprocessor Research Center of Peking Univ., China)
Abstract We propose a fast clock skew scheduling algorithm which minimizes clock period and enlarges the slacks of timing critical paths. To reduce the runtime of the timing analysis engine, our algorithm allows the sequential graph to be partly extracted. And the runtime of itself is almost linear to the size of the extracted sequential graph. Experimental results show its runtime is less than a minute for a design with more than ten thousands of flip-flops.

6A-3 (Time: 16:40 - 17:05)

Title Clock Tree Synthesis with Data-Path Sensitivity Matching
Author *Matthew R. Guthaus (Univ. of California, Santa Cruz, USA), Dennis Sylvester (Univ. of Michigan, USA), Richard B. Brown (Univ. of Utah, USA)
Abstract This paper investigates methods for minimizing the impact of process variation on clock skew using buffer and wire sizing. While most papers on clock trees ignore data-path circuit variations and most papers on data-path circuit optimization disregard clock tree variation, we consider both. Using both clock and data-path variations together, we present a novel sensitivity-matching algorithm that allows clock tree skews to be intentionally correlated with data-path sensitivities to ameliorate timing violations due to variation. Our statistical tuning shows an improvement in terms of expected clock skew and clock skew variation over previously published robust algorithms.

6A-4 (Time: 17:05 - 17:30)

Title Buffered Clock Tree Synthesis for 3D ICs Under Thermal Variations
Author Jacob Minz (Synopsys, USA), Xin Zhao, *Sung Kyu Lim (Georgia Inst. of Tech., USA)
Abstract In this paper, we study the buffered clock tree synthesis problem under thermal variations for 3D IC technology. Our major contribution is the Balanced Skew Theorem, which provides a theoretical background to efficiently construct a buffered 3D clock tree that minimizes and balances the skew values under two distinct non-uniform thermal profiles. Our clock tree synthesis algorithm named BURITO (Buffered Clock Tree With Thermal Optimization) first constructs a 3D abstract tree under the wirelength vs via-congestion tradeoff. This abstract tree is then embedded, buffered, and refined under the given non-uniform thermal profiles so that the temperature-dependent skews are minimized and balanced. Experimental results show that our algorithms significantly reduce and perfectly balance clock skew values with minimal wirelength overhead.
No Slides

6A-5 (Time: 17:30 - 17:43)

Title A Delay Model for Interconnect Trees Based on ABCD Matrix
Author *Guofei Zhou, Li Su, Depeng Jin, Lieguang Zeng (Tsinghua Univ., China)
Abstract The accuracy of interconnect delay estimations can be improved by the method presented in this paper, in which the first two moments are obtained with ABCD matrix and a stable model to incorporate effects of transport delay into the delay estimate is developed. Simulation results show that the method share the same accuracy with traditional methods when rise time delay is much longer than transport delay and more accurate when the two are of the same order.

6A-6 (Time: 17:43 - 17:56)

Title Analytical Model for the Impact of Multiple Input Switching Noise on Timing
Author Rajeshwary Tayade (Univ. of Texas, Austin, USA), *Sani Nassif (IBM, USA), Jacob Abraham (Univ. of Texas, Austin, USA)
Abstract The timing models used in current Static Timing Analysis tools characterize gate delays only for single input switching events. It is well known that the temporal proximity of signals arriving at different inputs causes significant variation in the gate delay. This variation in delay needs to be accounted for when selecting critical paths of a circuit. In this paper, a detailed analysis of Multiple Input Switching (MIS) behavior is presented that leads to a simple analytical model which can be used to estimate gate delay with MIS noise. The model presented requires minimum additional characterization effort, and can be employed in a statistical timing engine. The dynamic delay variability of a path caused due to MIS noise can be accurately estimated using the proposed model.
No Slides
Last Updated on: January 31, 2008