Session 7A: Reliable/Testable Design Techniques

7A-1 (Time: 10:15 - 10:40)

Title Soft Error Rate Reduction Using Redundancy Addition and Removal
Author *Kai-Chiang Wu, Diana Marculescu (Carnegie Mellon Univ., USA)
Abstract Due to current technology scaling trends such as shrinking feature sizes and reducing supply voltages, circuit reliability has become more susceptible to radiation-induced transient faults (soft errors). Soft errors, which have been a great concern in memories, are now a main factor in reliability degradation of logic circuits. In this paper, we propose a novel framework based on redundancy addition and removal (RAR) for soft error rate (SER) reduction. Several metrics and constraints are introduced to guide our proposed framework towards SER reduction in an efficient manner. Experimental results show that up to 70% reduction in output failure probability can be achieved with relatively low area overhead.

7A-2 (Time: 10:40 - 11:05)

Title Localized Random Access Scan: Towards Low Area and Routing Overhead
Author *Yu Hu, Xiang Fu, Xiaoxin Fan (Chinese Academy of Sciences, China), Hideo Fujiwara (Nara Inst. of Science and Technology, Japan)
Abstract Conventional random access scan (RAS) designs are expensive in hardware overhead. In this paper, we present a localized RAS architecture (LRAS) to address this issue. A novel scan cell structure, which has fewer transistors than multiplexer-type scan cell, is proposed to eliminate the global test enable signal and to localize the row and column enable signals. Experimental results demonstrate that LRAS has less area overhead than scan chain based designs, while outperforms the state-of-the-art RAS scheme in routing overhead.
No Slides

7A-3 (Time: 11:05 - 11:30))

Title A Design-for-Diagnosis Technique for Diagnosing Both Scan Chain Faults and Combinational Circuit Faults
Author Fei Wang, *Yu Hu, Huawei Li, Xiaowei Li (Chinese Academy of Sciences, China)
Abstract The amount of die area consumed by scan chains and scan control circuit can range from 15%~30%, and scan chain failures account for almost 50% of chip failures. As the conventional diagnosis process usually runs on the faulty free scan chain, scan chain faults may disable the diagnostic process, leaving large failure area to time-consuming failure analysis. In this paper, a design-for-diagnosis (DFD) technique is proposed to diagnose faulty scan chains precisely and efficiently, moreover, with the assistant of the proposed technique, the conventional logic diagnostic process can be carried on with faulty scan chains. The proposed approach is entirely compatible with conventional scan-based design. Previously proposed software-based diagnostic methods for conventional scan designs can still be applied to our design. Experiments on ISCAS'89 benchmark circuits are conducted to demonstrate the efficiency of the proposed DFD technique.

7A-4 (Time: 11:30 - 11:55)

Title GECOM: Test Data Compression Combined with All Unknown Response Masking
Author *Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ., Japan)
Abstract This paper introduces GECOM technology, a novel test compression method with seamless integration of test GEneration, test COmpression (i.e. integrated compression on scan stimulus and masking bits) and all unknown scan responses Masking for manufacturing test cost reduction. Unlike most of prior methods, the proposed method considers the unknown responses during ATPG procedure and selectively encodes the specified 1 or 0 bits (either 1s or 0s) in scan slices for compression while at the same time masks the unknown responses before sending them to the response compactor. The proposed GECOM technology consists of GECOM architecture and GECOM ATPG technique. In the GECOM architecture, for a circuit with N internal scan chains, only c tester channels, where $c = \lceil \log_2{N} \rceil + 2 $, are required. GECOM ATPG generates test patterns for the GECOM architecture thus not only the scan inputs could be efficiently compressed but also all the unknown responses would be masked. Experimental results on both benchmark circuits and real industrial designs indicated the effectiveness of the proposed GECOM technique.
Last Updated on: January 31, 2008