Session 7B: Communication and Interfaces

7B-1 (Time: 10:15 - 10:40)

Title Mixed Integer Linear Programming-Based Optimal Topology Synthesis of Cascaded Crossbar Switches
Author *Minje Jun (Yonsei Univ., Korea), Sungjoo Yoo (Samsung Electronics, Korea), Eui-Young Chung (Yonsei Univ., Korea)
Abstract We present a topology synthesis method for high performance System-on-Chip (SoC) design. Our method provides an optimal topology of on-chip communication network for the given bandwidth, latency, frequency and/or area constraints. The optimal topology consists of multiple crossbar switches and some of them can be connected in a cascaded fashion for higher clock frequency and/or area efficiency. Compared to previous works, the major contribution of our work is the exactness of the solution from two aspects. First, the solving method of our work is exact by employing the mixed integer linear programming (MILP) method. Second, we generalize the crossbar switch representation in MILP in order that the optimal topology can include any arbitrary sizes of crossbar switches together. The experimental results show that the topologies optimized for the clock frequency (area) give up to 37.3% (12.7%) improvements compared to the conventional single large crossbar switch networks for two industrial strength SoC designs.

7B-2 (Time: 10:40 - 11:05)

Title Automatic Interface Synthesis Based on the Classification of Interface Protocols of IPs
Author *ChangRyul Yun (Agency for Defense Development, Korea), DongSoo Kang (Chungnam National Univ., Korea), YoungHwan Bae, HanJin Cho (ETRI, Korea), KyoungSon Jhang (Chungnam Nat’l Univ., Korea)
Abstract In a System on a Chip (SoC) design, we use an IP-based design methodology to reduce design time. An interface circuit design is one of the most essential factors in IP-based design. However, it is not easy to generate interface circuits because IPs have various characteristics. For example, one IP may send only one outstanding address in a burst but another IP may need one address for each transfer in a burst. IPs also use different clock frequencies or different data widths. It is necessary to analyze the interface protocols of each IP to consider and resolve these differences during synthesis. In this paper, we categorize the various interface protocols and use the synthesis algorithm to select the appropriate structure based on the categorizations, clock frequencies, and data width differences of the IPs. Through the experiments, we show that we could automatically generate interface circuits for IPs with different clocks, different data widths, and no address concepts. Experiments also show the pros and cons of two structures based on the comparisons of the synthesis results of several IP pairs which could be employed between two alternative structures, namely, product FSM-based structure and FSMD-like structure.

7B-3 (Time: 11:05 - 11:30)

Title The Shining Embedded System Design Methodology Based on Self Dynamic Reconfigurable Architectures
Author C. A. Curino, *L. Fossati, V. Rana, F. Redaelli, M. D. Santambrogio, D. Sciuto (Politecnico di Milano, Italy)
Abstract Complex design, targeting System-on-Chip based on reconfigurable architectures, still lacks a generalized methodology allowing both the automatic derivation of a complete system solution able to fit into the final device, and mixed hardware-software solutions, exploiting partial reconfiguration capabilities. The Shining methodology organizes the input specification of a complex System-on-Chip design into three different components: hardware, reconfigurable hardware and software, each handled by dedicated sub-flows. A communication model guarantees reliable and seamless interfacing of the various components. The developed system, stand-alone or OS-based, is architecture-independent. The Shining flow reduces the time for system development, easing the design of complex hardware/software reconfigurable applications.

7B-4 (Time: 11:30 - 11:43)

Title Robust On-Chip Bus Architecture Synthesis for MPSoC Under Random Tasks Arrival
Author *Sujan Pandey (NXP Semiconductors Research, Netherlands), Rolf Drechsler (Univ. of Bremen, Germany)
Abstract A major trend in a modern system-on-chip design is a growing system complexity, which results in a sharp increase of communication traffic on the on-chip communication bus architectures. In a real-time embedded system, task arrival rate, inter-tasks arrival time, and data size to be transferred are not uniform over time. This is due to the partial re-configuration of an embedded system to cope with dynamic workload. In this context, the traditional application specific bus architectures may fail to meet the real-time constraints. Thus, to incorporate the random behavior of on-chip communication, this work proposes an approach to synthesize an on-chip bus architecture, which is robust for a given distributions of random tasks. The randomness of communication tasks is characterized by three main parameters which are average tasks arrival rate, average inter-tasks arrival time, and data size. For synthesis, an on-chip bus requirement is guided by the worst-case performance need, while the dynamic voltage scaling technique is used to save energy when the workload is low or timing slack is high. This, in turn, results in an effective utilization of communication resources under variable workload.
No Slides

7B-5 (Time: 11:43 - 11:56)

Title A Multi-Processor NoC Platform Applied on the 802.11i TKIP Cryptosystem
Author *Jung-Ho Lee, Sung-Rok Yoon, Kwang-Eui Pyun, Sin-Chong Park (ICU, Korea)
Abstract Since 2001, there have been a myriad of papers on systematic analysis of Multi-Processor System on Chip (MPSoC) and Network on Chip (NoC). Nevertheless, we only have a few of their practical application. Till now, main interest of researchers has been to adapt NoC to the communication intensive multimedia system like H.263. However, this paper attempts to expand the domain of NoC platform to one of the wireless security algorithms (TKIP), because its inter-component transaction pattern shows considerable characteristic for NoC. This paper consists of the explanation on operational sequence of the algorithm in chosen architecture and the brief illustration of important composing NoC blocks (Network Interface, Router).
Last Updated on: January 31, 2008