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The 15th Asia and South Pacific Design Automation Conference

Session 4D  University LSI Design Contest
Time: 10:30 - 12:10 Wednesday, January 20, 2010
Location: Room 101D
Organizers: Jiun-In Guo (National Chung Cheng Univ., Taiwan), Masanori Hariyama (Tohoku Univ., Japan)

4D-1 (Time: 10:30 - 10:35)
TitleChecker-Pattern and Shared Two Pixels LOFIC CMOS Image Sensors
Author*Yoshiaki Tashiro, Shun Kawada, Shin Sakai, Shigetoshi Sugawa (Tohoku Univ., Japan)
Pagepp. 343 - 344
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4D-2 (Time: 10:35 - 10:40)
TitleA CMOS Image Sensor With 2.0-e- Random Noise and 110-ke- Full Well Capacity Using Column Source Follower Readout Circuits
Author*Takahiro Kohara, Wonghee Lee (Tohoku Univ., Japan), Koichi Mizobuchi (Texas Instruments Japan, Japan), Shigetoshi Sugawa (Tohoku Univ., Japan)
Pagepp. 345 - 346
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4D-3 (Time: 10:40 - 10:45)
TitleCheckered White-RGB Color LOFIC CMOS Image Sensor
Author*Shun Kawada, Shin Sakai, Yoshiaki Tashiro, Shigetoshi Sugawa (Tohoku Univ., Japan)
Pagepp. 347 - 348
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4D-4 (Time: 10:45 - 10:50)
TitleA Versatile Recognition Processor for Sensor Network Applications
Author*Risako Takashima, Hanai Yuya, Yuichi Hori, Tadahiro Kuroda (Keio Univ., Japan)
Pagepp. 349 - 350
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4D-5 (Time: 10:50 - 10:55)
TitleA 2-6 GHz Fully Integrated Tunable CMOS Power Amplifier for Multi-Standard Transmitters
AuthorDaisuke Imanishi, *JeeYoung Hong, Kenichi Okada, Akira Matsuzawa (Tokyo Inst. of Tech., Japan)
Pagepp. 351 - 352
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4D-6 (Time: 10:55 - 11:00)
TitleAn Embedded Debugging/Performance Monitoring Engine for a Tile-based 3D Graphics SoC Development
Author*Liang-Bi Chen, Tsung-Yu Ho, Jiun-Cheng Ju, Cheng-Lung Chiang, Chung-Nan Lee, Ing-Jer Huang (National Sun Yat-Sen Univ., Taiwan)
Pagepp. 353 - 354
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4D-7 (Time: 11:00 - 11:05)
TitleCascaded Time Difference Amplifier using Differential Logic Delay Cell
Author*Shingo Mandai, Toru Nakura, Makoto Ikeda, Kunihiro Asada (Univ. of Tokyo, Japan)
Pagepp. 355 - 356
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4D-8 (Time: 11:05 - 11:10)
TitleBuilt-in Self At-Speed Delay Binning and Calibration Mechanism in Wireless Test Platform
AuthorChen-I Chung, Jyun-Sian Jhou, *Ching-Hwa Cheng (Feng Chia Univ., Taiwan)
Pagepp. 357 - 358
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4D-9 (Time: 11:10 - 11:15)
TitleDynamic Voltage Domain Assignment Technique for Low Power Performance Manageable Cell Based Design
AuthorElone Lee, Feng-Tso Chien, *Ching-Hwa Cheng (Feng Chia Univ., Taiwan), Jiun-In Guo (National Chung Cheng Univ., Taiwan)
Pagepp. 359 - 360
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4D-10 (Time: 11:15 - 11:20)
TitleAdaptive Performance Control with Embedded Timing Error Predictive Sensors for Subthreshold Circuits
Author*Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye (Osaka Univ., Japan)
Pagepp. 361 - 362
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4D-12 (Time: 11:20 - 11:25)
TitleA 60GHz Direct-Conversion Transmitter in 65nm CMOS Technology
Author*Naoki Takayama, Kouta Matsushita, Shogo Ito, Ning Li, Kenichi Okada, Akira Matsuzawa (Tokyo Inst. of Tech., Japan)
Pagepp. 363 - 364
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4D-13 (Time: 11:25 - 11:30)
TitleAn Electrically Adjustable 3-Terminal Regulator with Post-Fabrication Level-Trimming Function
Author*Hiroyuki Morimoto, Hiroki Koike, Kazuyuki Nakamura (Kyushu Inst. of Tech., Japan)
Pagepp. 365 - 366
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4D-14 (Time: 11:30 - 11:35)
TitleFine Resolution Double Edge Clipping with Calibration Technique for Built-In At-Speed Delay Testing
AuthorChen-I Chung, Shuo-Wen Chang, Feng-Tso Chien, *Ching-Hwa Cheng (Feng Chia Univ., Taiwan)
Pagepp. 367 - 368
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4D-15 (Time: 11:35 - 11:40)
TitleGeyser-1: A MIPS R3000 CPU core with fine-grained run-time Power Gating
AuthorDiasuke Ikebuchi, Naomi Seki, Yuu Kojima, *Masahiro Kamata, Zhao Lei, Hideharu Amano (Keio Univ., Japan), Toshiki Shirai, Satoshi Koyama, Tatsunori Hashida, Yusuke Umahashi, Hiroki Masuda, Kimiyoshi Usami (Shibaura Inst. of Tech., Japan), Seidai Takeda, Hiroshi Nakamura (Univ. of Tokyo, Japan), Mitaro Namiki (Univ. of Agri. and Tech., Japan), Masaaki Kondo (Univ. of Electro-Communications, Japan)
Pagepp. 369 - 370
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4D-16 (Time: 11:40 - 11:45)
TitleA WiMAX Turbo Decoder with Tailbiting BIP Architecture
Author*Hiroaki Arai, Naoto Miyamoto, Koji Kotani (Tohoku Univ., Japan), Hisanori Fujisawa (Fujitsu Laboratories Ltd., Japan), Takashi Ito (Tohoku Univ., Japan)
Pagepp. 371 - 372
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4D-17 (Time: 11:45 - 11:50)
TitleTemporal Circuit Partitioning for a 90nm CMOS Multi-Context FPGA and its Delay Measurement
Author*Naoto Miyamoto, Tadahiro Ohmi (Tohoku Univ., Japan)
Pagepp. 373 - 374
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4D-18 (Time: 11:50 - 11:55)
TitleDesign and Chip Implementation of an Instruction Scheduling Free Ubiquitous Processor
Author*Masa-aki Fukase, Ryosuke Murakami, Tomoaki Sato (Hirosaki Univ., Japan)
Pagepp. 375 - 376
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4D-19 (Time: 11:55 - 12:00)
TitleMUCCRA-3: A Low Power Dynamically Reconfigurable Processor Array
AuthorYoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tunbunheng, Yoshihiro Yasuda, *Masayuki Kimura, Hideharu Amano (Keio Univ., Japan)
Pagepp. 377 - 378
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4D-20 (Time: 12:00 - 12:05)
TitleRapid Prototyping on a Structured ASIC Fabric
Author*Steve C.L. Yuen, Yan-Qing Ai, Brian P.W. Chan, Thomas C.P. Chau, Sam M.H. Ho, Oscar K.L. Lau, Kong-Pang Pun (Chinese Univ. of Hong Kong, Hong Kong), Philip H.W. Leong (Univ. of Sydney, Australia), Oliver C.S. Choy (Chinese Univ. of Hong Kong, Hong Kong)
Pagepp. 379 - 380
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4D-21 (Time: 12:05 - 12:10)
TitleA High Performance Low Complexity Joint Transceiver for Closed-Loop MIMO Applications
AuthorJian-Lung Tzeng, Chien-Jen Huang, *Yu-Han Yuan, Hsi-Pin Ma (National Tsing Hua Univ., Taiwan)
Pagepp. 381 - 382
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