Title | Checker-Pattern and Shared Two Pixels LOFIC CMOS Image Sensors |
Author | *Yoshiaki Tashiro, Shun Kawada, Shin Sakai, Shigetoshi Sugawa (Tohoku Univ., Japan) |
Page | pp. 343 - 344 |
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Title | A CMOS Image Sensor With 2.0-e- Random Noise and 110-ke- Full Well Capacity Using Column Source Follower Readout Circuits |
Author | *Takahiro Kohara, Wonghee Lee (Tohoku Univ., Japan), Koichi Mizobuchi (Texas Instruments Japan, Japan), Shigetoshi Sugawa (Tohoku Univ., Japan) |
Page | pp. 345 - 346 |
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Title | Checkered White-RGB Color LOFIC CMOS Image Sensor |
Author | *Shun Kawada, Shin Sakai, Yoshiaki Tashiro, Shigetoshi Sugawa (Tohoku Univ., Japan) |
Page | pp. 347 - 348 |
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Title | A Versatile Recognition Processor for Sensor Network Applications |
Author | *Risako Takashima, Hanai Yuya, Yuichi Hori, Tadahiro Kuroda (Keio Univ., Japan) |
Page | pp. 349 - 350 |
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Title | A 2-6 GHz Fully Integrated Tunable CMOS Power Amplifier for Multi-Standard Transmitters |
Author | Daisuke Imanishi, *JeeYoung Hong, Kenichi Okada, Akira Matsuzawa (Tokyo Inst. of Tech., Japan) |
Page | pp. 351 - 352 |
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Title | An Embedded Debugging/Performance Monitoring Engine for a Tile-based 3D Graphics SoC Development |
Author | *Liang-Bi Chen, Tsung-Yu Ho, Jiun-Cheng Ju, Cheng-Lung Chiang, Chung-Nan Lee, Ing-Jer Huang (National Sun Yat-Sen Univ., Taiwan) |
Page | pp. 353 - 354 |
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Title | Cascaded Time Difference Amplifier using Differential Logic Delay Cell |
Author | *Shingo Mandai, Toru Nakura, Makoto Ikeda, Kunihiro Asada (Univ. of Tokyo, Japan) |
Page | pp. 355 - 356 |
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Title | Built-in Self At-Speed Delay Binning and Calibration Mechanism in Wireless Test Platform |
Author | Chen-I Chung, Jyun-Sian Jhou, *Ching-Hwa Cheng (Feng Chia Univ., Taiwan) |
Page | pp. 357 - 358 |
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Title | Dynamic Voltage Domain Assignment Technique for Low Power Performance Manageable Cell Based Design |
Author | Elone Lee, Feng-Tso Chien, *Ching-Hwa Cheng (Feng Chia Univ., Taiwan), Jiun-In Guo (National Chung Cheng Univ., Taiwan) |
Page | pp. 359 - 360 |
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Title | Adaptive Performance Control with Embedded Timing Error Predictive Sensors for Subthreshold Circuits |
Author | *Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye (Osaka Univ., Japan) |
Page | pp. 361 - 362 |
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Title | A 60GHz Direct-Conversion Transmitter in 65nm CMOS Technology |
Author | *Naoki Takayama, Kouta Matsushita, Shogo Ito, Ning Li, Kenichi Okada, Akira Matsuzawa (Tokyo Inst. of Tech., Japan) |
Page | pp. 363 - 364 |
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Title | An Electrically Adjustable 3-Terminal Regulator with Post-Fabrication Level-Trimming Function |
Author | *Hiroyuki Morimoto, Hiroki Koike, Kazuyuki Nakamura (Kyushu Inst. of Tech., Japan) |
Page | pp. 365 - 366 |
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Title | Fine Resolution Double Edge Clipping with Calibration Technique for Built-In At-Speed Delay Testing |
Author | Chen-I Chung, Shuo-Wen Chang, Feng-Tso Chien, *Ching-Hwa Cheng (Feng Chia Univ., Taiwan) |
Page | pp. 367 - 368 |
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Title | Geyser-1: A MIPS R3000 CPU core with fine-grained run-time Power Gating |
Author | Diasuke Ikebuchi, Naomi Seki, Yuu Kojima, *Masahiro Kamata, Zhao Lei, Hideharu Amano (Keio Univ., Japan), Toshiki Shirai, Satoshi Koyama, Tatsunori Hashida, Yusuke Umahashi, Hiroki Masuda, Kimiyoshi Usami (Shibaura Inst. of Tech., Japan), Seidai Takeda, Hiroshi Nakamura (Univ. of Tokyo, Japan), Mitaro Namiki (Univ. of Agri. and Tech., Japan), Masaaki Kondo (Univ. of Electro-Communications, Japan) |
Page | pp. 369 - 370 |
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Title | A WiMAX Turbo Decoder with Tailbiting BIP Architecture |
Author | *Hiroaki Arai, Naoto Miyamoto, Koji Kotani (Tohoku Univ., Japan), Hisanori Fujisawa (Fujitsu Laboratories Ltd., Japan), Takashi Ito (Tohoku Univ., Japan) |
Page | pp. 371 - 372 |
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Title | Temporal Circuit Partitioning for a 90nm CMOS Multi-Context FPGA and its Delay Measurement |
Author | *Naoto Miyamoto, Tadahiro Ohmi (Tohoku Univ., Japan) |
Page | pp. 373 - 374 |
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Title | Design and Chip Implementation of an Instruction Scheduling Free Ubiquitous Processor |
Author | *Masa-aki Fukase, Ryosuke Murakami, Tomoaki Sato (Hirosaki Univ., Japan) |
Page | pp. 375 - 376 |
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Title | MUCCRA-3: A Low Power Dynamically Reconfigurable Processor Array |
Author | Yoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tunbunheng, Yoshihiro Yasuda, *Masayuki Kimura, Hideharu Amano (Keio Univ., Japan) |
Page | pp. 377 - 378 |
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Title | Rapid Prototyping on a Structured ASIC Fabric |
Author | *Steve C.L. Yuen, Yan-Qing Ai, Brian P.W. Chan, Thomas C.P. Chau, Sam M.H. Ho, Oscar K.L. Lau, Kong-Pang Pun (Chinese Univ. of Hong Kong, Hong Kong), Philip H.W. Leong (Univ. of Sydney, Australia), Oliver C.S. Choy (Chinese Univ. of Hong Kong, Hong Kong) |
Page | pp. 379 - 380 |
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Title | A High Performance Low Complexity Joint Transceiver for Closed-Loop MIMO Applications |
Author | Jian-Lung Tzeng, Chien-Jen Huang, *Yu-Han Yuan, Hsi-Pin Ma (National Tsing Hua Univ., Taiwan) |
Page | pp. 381 - 382 |
Detailed information (abstract, keywords, etc) | |
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