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ASP-DAC 2006 Archives
5A-1
| Title | Depth-Driven Verification of Simultaneous Interfaces |
| Author | *Ilya Wagner, Valeria Bertacco, Todd Austin (Univ. of Michigan, United States) |
| Abstract | The verification of modern computing systems has grown to dominate the cost of system design, often with limited success as designs continue to be released with latent bugs. This trend is accelerated with the advent of highly integrated system-on-a-chip (SoC) designs, which feature multiple complex subcomponents connected by simultaneously active interfaces. In this paper, we introduce a closed-loop feedback technique targeting the verification of multiple components connected by parallel interfaces. We utilize an environment with hierarchical Markov models, where top-level submodels specify overarching simulation goals of the system, while lower-level submodels specify the detailed component-level input generation. Test accuracy is improved through the use of depth-driven random test generation. The approach allows users to specify correctness properties and key activity nodes in the design to be exercises. We examine three non-trivial designs, two microprocessors and a chip-multiprocessor router switch, and we demonstrate that our technique finds many more bugs than constrained-random test generation technique and reduces the simulation effort in half, compared to previous Markov-model based solutions. |
| Slides (pdf file) | 5A-1 |
5A-2
| Title | FSM-Based Transaction-Level Functional Coverage for Interface Compliance Verification |
| Author | *Man-Yun Su, Che-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou (Department of Electronics Engineering, National Chiao Tung University, Taiwan) |
| Abstract | Interface compliance verification plays a very important role in modern SoC designs. In order to perform a quantitative analysis of simulation completeness, adequate coverage metrics are mandatory. In this paper, we propose a finite state machine (FSM) based transaction-level functional coverage methodology for interface compliance verification. A language, State-Oriented Language (SOL), is developed to specify functional transactions mainly at the higher FSM level instead of lower logic or signal level. By utilizing SOL, it is simple and rigorous to specify interesting transactions from the specification FSM of the target interface protocol. Experimental results show that the proposed methodology can effectively improve the verification quality as well as increase the efficiency of regression verification. |
| Slides (pdf file) | 5A-2 |
5A-3
| Title | Hardware Debugging Method Based on Signal Transitions and Transactions |
| Author | *Nobuyuki Ohba, Kohji Takano (IBM Japan Ltd., Japan) |
| Abstract | This paper proposes a hardware design debugging method, Transition and Transaction Tracer (TTT), which probes and records the signals of interest for a long time, hours, days, or even weeks, without a break. It compresses the captured data in real time and stores it in a state transition format in memory. It can be programmed to generate a trigger for a logic analyzer when it detects certain transitions. The visualizer, which shows the captured data in the matrix, timing-chart, and state-transition diagram formats, helps the engineer effectively find bugs. |
| Slides (pdf file) | 5A-3 |
5A-4
| Title | Cycle Error Correction in Asynchronous Clock Modeling for Cycle-Based Simulation |
| Author | *Junghee Lee, Joonhwan Yi (Samsung Electronics, Republic of Korea) |
| Abstract | As the complexity of SoCs is increasing, hardware/software co-verification becomes an important part of system verification. C-level cycle-based simulation could be an efficient methodology for system verification because of its fast simulation speed. The cycle-based simulation has a limitation in using asynchronous clocks that causes inherent cycle errors. In order to reuse the output of a C-level cycle-based simulation for the verification of a lower level model, the C-level model should be cycle-accurate with respect to the lower level model. In this paper a cycle error correction technique is presented for two asynchronous clock models. An example design is devised to show the effectiveness of the proposed method. Our experimental results show that the fast speed of cycle-based simulation can be fully exploited without sacrificing the cycle accuracy. |
| Slides (pdf file) | 5A-4 |
5A-5
| Title | A Fast Logic Simulator Using a Look Up Table Cascade Emulator |
| Author | *Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura (Kyushu Institute of Technology, Japan) |
| Abstract | This paper shows a new type of a cycle-based logic simulation method using a Look-Up Table (LUT) cascade emulator. The method first transforms a given circuit into LUT cascades through BDD (Binary Decision Diagram). Then, it stores LUT data to the memory of an LUT cascade emulator. Next, it generates the C code representing the control circuit of the LUT cascade emulator. And, finally, it converts the C code into the execution code. This method is compared with a Levelized Compiled Code (LCC) simulator with respect to the simulation time and setup time. Although we used standard PC to simulate the circuit, experimental results show that this method is 12-64 times faster than the LCC. |
| Slides (pdf file) | 5A-5 |