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ASP-DAC 2006 Archives
6B-1
| Title | Reusable Component IP Design using Refinement-based Design Environment |
| Author | *Sanggyu Park, Sang-Yong Yoon, Soo-Ik Chae (Seoul National University, Republic of Korea) |
| Abstract | We propose a method for enhancing the reusability of the component IPs by exploiting our refinement-based design environment, SoCBase-DE. In this method, a computation designer captures the computation part of the function and then a system designer constructs the communication part of the function to be best fit to the system using the SoCBase-DE. This method allows the reuse-centric design environment to be more effective and attractive. We evaluated this method on the design of a H.264 Decoder System. |
| Slides (pdf file) | 6B-1 |
6B-2
| Title | An Interface-Circuit Synthesis Method with Configurable Processor Core in IP-Based SoC Designs |
| Author | *Shunitsu Kohara, Naoki Tomono, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda University, Japan) |
| Abstract | In SoC designs, efficient communication between the hardware IPs and the on-chip processor becomes very important, however the interface is usually affacted by the processor core specification. Thus in this paper, we focus on developing an efficient interface circuit architecture for the communications between the on-chip processor and embedded hardware IP cores. we also propose a method to synthesize it. Experimental results show that our method could obtain optimal interface circuits and works well through designing a MPEG-4 encode application. |
| Slides (pdf file) | 6B-2 |
6B-3
| Title | A Real-Time and Bandwidth Guaranteed Arbitration Algorithm for SoC Bus Communication |
| Author | Chien-Hua Chen, *Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou (Department of Electronics Engineering, National Chiao Tung University , Taiwan) |
| Abstract | In shared SoC bus systems, arbiters are usually adopted to solve bus contentions with various kinds of arbitration algorithms. We propose an arbitration algorithm, RT_lottery, which is designed to meet both hard real-time and bandwidth requirements. For fast evaluation and exploration, we use high abstract-level models in our system simulation environment to generate parameters for our configurable arbiter. The experimental results show that RT_lottery can meet all hard real-time requirements and perform very well in bandwidth allocation. The results also show that RT_lottery outperforms several commonly-used arbitration algorithms today. |
| Slides (pdf file) | 6B-3 |
6B-4
| Title | Hierarchical Memory Size Estimation for Loop Fusion and Loop Shifting in Data-Dominated Applications |
| Author | *Qubo Hu (University of Trondheim, Norway), Arnout Vandecappelle, Martin Palkovic (IMEC, Belgium), Per Gunnar Kjeldsberg (University of Trondheim, Norway), Erik Brockmeyer, Francky Catthoor (IMEC, Belgium) |
| Abstract | Loop fusion and loop shifting are important transformations for improving data locality to reduce the number of costly accesses to off-chip memories. Since exploring the exact platform mapping for all the loop transformation alternatives is a time consuming process, heuristics steered by improved data locality are generally used. However, pure locality estimates do not sufficiently take into account the hierarchy of the memory platform. This paper presents a fast, incremental technique for hierarchical memory size requirement estimation for loop fusion and loop shifting at the early loop transformations design stage. As the exact memory platform is often not yet defined at this stage, we propose a platform-independent approach which reports the Pareto-optimal trade-off points for scratch-pad memory size and off-chip memory accesses. The estimation comes very close to the actual platform mapping. Experiments on realistic test-vehicles confirm that. It helps the designer or a tool to find the interesting loop transformations that should then be investigated in more depth afterward. |
| Slides (pdf file) | 6B-4 |
6B-5
| Title | A Novel Instruction Scratchpad Memory Optimization Method based on Concomitance Metric |
| Author | Andhi Janapsatya, Aleksandar Ignjatovic, *Sri Parameswaran (The University of New South Wales, Australia) |
| Abstract | Scratchpad memory has been introduced as a replacement for cache memory as it improves performance, and significantly reduces energy consumption of the memory hierarchy of certain embedded systems. This paper deals with optimization of the instruction memory scratchpad based on a novel methodology that uses a metric which we call concomitance. This metric is used to find basic blocks which are executed frequently and in close proximity in time. Once such blocks are found, they are copied into the scratchpad memory at appropriate times; this is achieved using a special instruction inserted into the code at appropriate places. For a set of benchmarks taken from Mediabench, our scratchpad system reduced energy consumption by an average of 49.4% compared to the cache system, and by 30.7% on average when compared to the state of the art scratchpad system, while improving the overall performance. Compared to the state of the art method, the number of instructions copied into the scratchpad memory from the main memory is reduced by 90.4%. |
| Slides (pdf file) | 6B-5 |