Session 9D: Designers' Forum (Panel) Best Ways to Use Billions of Devices on a Chip


Title (Panel Discussion) Best Ways to Use Billions of Devices on a Chip
Author Moderator: Grant Martin (Tensilica, USA), Panelists: Deming Chen (Univ. of Illinois, Urbana-Champaign, USA), Nikil Dutt (Univ. of California, Irvine, USA), Joerg Henkel (Karlsruhe Univ., Germany), Kyungho Kim (Samsung Electronics, Korea), Kazutoshi Kobayashi (Kyoto Univ., Japan)
Abstract We all know that Moore's law is good for at least a few more generations of silicon process, and this will give rise to many integrated circuits having billions of transistors on them. The leading 45 nm processors being announced are getting close to a billion transistors as of 2007. But how can we best use these devices in the future? Integrating more and more features and functions onto SoCs may not be the optimal use for all of these billions of resources. Indeed, to even have a working device at 45, 32, 22 and 16 nm may require new architectures and new structures to be incorporated.


Title (Invited Paper) VEBoC: Variation and Error-Aware Design for Billions of Devices on a Chip
Author Shoaib Akram, Scott Cromar, Gregory Lucas, Alexandros Papakonstantinou, *Deming Chen (Univ. of Illinois, Urbana-Champaign, USA)
Abstract Billions of devices on a chip is around the corner and the trend of deep submicron (DSM) technology scaling will continue for at least another decade. Meanwhile, designers also face severe on-chip parameter variations, soft/hard errors, and high leakage power. How to use these billions of devices to deliver power-efficient, high-performance, and yet error-resilient computation is a challenging task. In this paper, we attempt to demonstrate some of our perspectives to address these critical issues.


Title (Invited Paper) Quo Vadis, BTSoC (Billion Transistor SoC)?
Author *Nikil Dutt (Univ. of California, Irvine, USA)
Abstract Billion Transistor Systems-on-Chip (BTSoCs) present designers with a classic case of the "embarrassment-of-riches" syndrome: with so many devices at one's disposal, designers may be tempted to integrate functionality willy-nilly, with no strategic rethinking of what this level of integration can both afford, as well as achieve. While many advocate "business-asusual" - including ad-hoc integration of functionality to achieve application-specific or domain-dependent designs - I believe BTSoCs present us with some opportunities for a paradigm shift in the architectural strategies and design processes for designing such complex chips.


Title (Invited Paper) Best Ways to use Billions of Devices on a Chip
Author *Jeorg Henkel (Karlsruhe Univ., Germany)


Title (Invited Paper) Best Ways to use Billions of Devices on a Wireless Mobile SoC
Author *KyungHo Kim (Samsung Electronics, Korea)
Abstract A rapid growth in the field of Information Technologies (IT) over the last decade gave us unimaginable possibilities and lots of convenience in our life, i.e. highspeed Internet, mobile-TV, High-definition digital TV, 3D-gaming, mobile multimedia player, Ultra-Mobile PC and so on. Nowadays, the technology is even exceeding market demands. Apple produced 160GB iPod which stores 40,000 songs. Samsung showed a world-first mobile phone with 10Megapixel camera on it. HSDPAbased video telephony service was commercialized in Korea.


Title (Invited Paper) Best Ways to Use Billions of Devices on a Chip - Error Predictive, Defect Tolerant and Error Recovery Designs
Author *Kazutoshi Kobayashi, Hidetoshi Onodera (Kyoto Univ., Japan)
Abstract Error rates on an LSI are increasing accord-ing to the Moore's law. Now is the time to start incorporat-ing error-tolerant design methodologies. This paper intro-duces sources of failures in semiconductor devices, levels of dependability according to applications of devices and some circuit-level techniques to detect or recover faults af-ter shipping.
Last Updated on: January 31, 2008