The 15th Asia and South Pacific Design Automation Conference
Technical Program

Remark: The presenter of each paper is marked with "*".

Technical Program: SIMPLE version DETAILED version with abstract One Page (Not Separated) version

Author Index: HERE

Session Schedule

Tuesday, January 19, 2010

Room 101A	Room 101B	Room 101C	Room 101D
Op (Room 101) Opening 8:30 - 9:00
1K (Room 101) Keynote Session I 9:00 - 10:00
2K (Room 101) Keynote Session II 10:20 - 11:20
3K (Room 101) Keynote Session III 11:20 - 12:20
1A Embedded Systems Design Techniques 13:30 - 15:10	1B Advanced Model Order Reduction Technique 13:30 - 15:10	1C Logic Synthesis 13:30 - 15:10	1D Special Session: Techniques for Efficient Energy Harvesting and Generation for Portable and Embedded Systems 13:30 - 15:10
2A Memory Management and Compiler Techniques 15:30 - 17:10	2B Power and Signal Integrity 15:30 - 17:10	2C System-level Simulation 15:30 - 17:10	2D Special Session: 3D Integration and Networks on Chips 15:30 - 17:10

Wednesday, January 20, 2010

Room 101A	Room 101B	Room 101C	Room 101D
3A Emerging Memories and 3D ICs 8:30 - 10:10	3B Macromodeling and Verification of Analog Systems 8:30 - 10:10	3C System-level Modelling and Analysis 8:30 - 10:10	3D Special Session: Recent Advancement in Post-silicon Validation 8:30 - 10:10
4A New Techniques for Beyond-die Routing 10:30 - 12:10	4B Analog Layout and Testing 10:30 - 12:10	4C New Techniques in Technology Mapping 10:30 - 12:10	4D University LSI Design Contest 10:30 - 12:10
5A Clock Network Analysis and Optimization 13:30 - 15:10	5B Test Solutions for Emerging Applications 13:30 - 15:10	5C Power, Performance and Reliability in SoC Design 13:30 - 15:10	5D Designers' Forum: State-of-the-art SoCs 13:30 - 15:10
6A Advances in Modern Clock Tree Routing 15:30 - 17:10	6B Timing-related Testing and Diagnosis 15:30 - 17:10	6C Application-specific NoC Design 15:30 - 17:10	6D Designers' Forum: Is 3D Integration an Opportunity or Just a Hype? 15:30 - 17:10

Thursday, January 21, 2010

Room 101A	Room 101B	Room 101C	Room 101D
7A Modern Floorplanning and Placement Techniques 8:30 - 10:10	7B Power Optimization and Estimation in the DSM Era 8:30 - 10:10	7C Design Verification and Debugging 8:30 - 10:10	7D Special Session: Dependable Silicon Design with Unreliable Components 8:30 - 10:10
8A DFM1: Patterning and Physical Design 10:30 - 12:10	8B Design and Verification for Process Variation Issues 10:30 - 12:10	8C New Advances in High-level Synthesis 10:30 - 12:10	8D Special Session: ESL: Analysis and Synthesis of Multi-core Systems 10:30 - 12:10
9A DFM2: Variation Modeling 13:30 - 15:10	9B Power Grid Analysis 13:30 - 15:10	9C High-level Synthesis and Optimization for Performance and Power 13:30 - 15:10	9D Designers' Forum: ESL, The Road to Glory, Or Is It Not? Real Stories about Using ESL Design Methodology in Product Development 13:30 - 15:10
10A DFM3: Robust Design 15:30 - 17:10	10B Emerging Circuits and Architectures 15:30 - 17:10	10C System-level MPSoC Analysis and Optimization 15:30 - 17:10	10D Designers' Forum: Embedded Software Development for Multi-Processor Systems-on-Chip 15:30 - 17:10