Keynote Addresses

Keynote I

More Moore, More than Moore, More People

Tadahiro Kuroda

University of Tokyo, Japan

The sustainable development of a data-driven society requires solving the energy crisis created by the proliferation of semiconductors (by developing green technology). Therefore, the semiconductor industry is entering a new era where it shifts focus from general-purpose chips with high production efficiency to specialized chips with high energy efficiency. While the general-purpose chip is a competition of device manufacturing (capital), the specialized chip is a competition of design (knowledge). As a result, innovation in the new era requires the democratization of semiconductors, in other words, the ability of more people to develop specialized chips. For that reason, an agile development platform is required that can develop a specialized chip using a combination of automated design and semi-custom manufacturing at 1/10 the time and cost. By following the 80-Point Score Principle (targeting good enough but not perfect score) and iterating development and improvement in a high-speed cycle, it is possible for many more people to rapidly develop a system that highly integrates hardware and software. By adding More People to More Moore and More than Moore of nanotechnology, democratization will drive the creation of an intellectual society.

Tadahiro Kuroda received the Ph.D. degree in electrical engineering from the University of Tokyo, Tokyo, Japan, in 1999.
 In 1982, he joined Toshiba Corporation. From 1988 to 1990, he was a Visiting Scholar with the University of California, Berkeley, where he conducted research in the field of VLSI CAD. In 1990, he was back to Toshiba, and engaged in the research and development of BiCMOS ASICs, ECL ASICs, and high-speed low-power CMOS LSIs. He invented a Variable Threshold-voltage CMOS (VTCMOS) technology to control VTH through substrate bias, and applied it to a DCT core processor in 1995. He also developed a Variable Supply-voltage scheme to control VDD by an embedded DC-DC converter, and employed it to a microprocessor core and an MPEG-4 chip in 1997. He left Toshiba to join Keio University in 2000, and became a full professor in 2002. He was the Mackay Professor at the University of California, Berkeley, in 2007. He invented a ThruChip Interface (TCI) by using magnetic coupling for communications among stacked chips in 2008, and a Transmission Line Coupler (TLC) by using electromagnetic coupling for communications among stacked PCBs in 2012. He left Keio to join the University of Tokyo in 2019. He is the director of Systems Design Lab (d.lab) at the University of Tokyo, and the chairman of Research Association for Advanced Systems (RaaS). He has published more than 450 papers, including 38 ISSCC papers, 29 VLSI Symposia papers, 19 CICC papers and 18 A-SSCC papers. He wrote 30 books/chapters and filed more than 200 patents.
 Dr. Kuroda is an IEEE Fellow, an IEICE Fellow, and a chair of Symposium on VLSI Technology and Circuits. He was an elected AdCom member of two terms. He was a recipient of the 2005 P&I Patent of the Year Award, the 2007 ASP-DAC Best Design Award, the 2009 IEICE Achievement Award, and the 2011 IEICE Society Award. He served as a Steering Committee Chair for A-SSCC, a Vice Chair for ASP-DAC, sub-committee chairs for A-SSCC, ICCAD, SSDM, and VLSI-DAT, and TPC members for ISSCC, Symposium on VLSI Circuits, CICC, DAC, ASPDAC, ISLPED, SSDM, ISQED, and other international conferences. He was a Distinguished Lecturer and a representative of Region 10 for the IEEE Solid-State Circuits Society.

Keynote II

Analog synthesis 3.0: AI/ML to boost automated design and test of analog/mixed-signal ICs

Georges G.E. Gielen

Georges G.E. Gielen

KU Leuven, Belgium

Analog/mixed-signal integrated circuits remain indispensable in electronics applications that interface the physical with the cyber world. But whereas digital circuits are largely synthesized through EDA software, the design of analog circuits in industry is surprisingly mainly still handcrafted, resulting in low design productivity with long and error-prone design cycles and high development costs. The showstopper for current analog synthesis tools is their need for proper and often circuit-specific design heuristics and constraints to be entered explicitly by designers in order to handle the humongous solution space and to steer the circuit and layout optimizations towards acceptable solutions. This keynote will present an analog synthesis 3.0 methodology based on advanced machine learning (ML) techniques to self-learn and then exploit the design expertise and constraints from available completed designs. Such innovations may finally enable to fully automate analog circuit design without human designer in the loop. The second AI for CAD application that will be presented is in analog test program development where ML methods will be shown to boost analog fault coverage, also for latent defects.

Georges G.E. Gielen received the MSc and PhD degrees in Electrical Engineering from the Katholieke Universiteit Leuven (KU Leuven), Belgium, in 1986 and 1990, respectively. He currently is Full Professor in the MICAS research division at the Department of Electrical Engineering (ESAT) at KU Leuven. From August 2013 until July 2017 he served as Vice-Rector for the Group of Sciences, Engineering and Technology. He was visiting professor at UC Berkeley and Stanford University. Since 2020 he is Chair of the Department of Electrical Engineering (ESAT) at KU Leuven.
 His research interests are in the design of analog and mixed-signal integrated circuits, and especially in analog and mixed-signal CAD tools and design automation, including modeling, simulation, optimization and synthesis as well as testing. He is a frequently invited speaker/lecturer and coordinator/partner of several (industrial) research projects in this area, including an ERC Advanced Grant. He has (co-)authored 10 books and more than 700 publications in edited books, international journals and conference proceedings. He is a 1997 Laureate of the Belgian Royal Academy of Sciences, Literature and Arts in the discipline of Engineering. He is Fellow of the IEEE since 2002, and received the IEEE CAS Mac Van Valkenburg award in 2015 and the IEEE CAS Charles Desoer award in 2020, as well as the EDAA Achievement Award in 2021. He is an elected member of the Academia Europaea.

Keynote III

Innovation by Design and Technology Co-Optimization

Mr. Takuya Yasui

Takuya Yasui

TSMC Japan Design Center, Japan

The semiconductor industry has been challenging transistor energy efficiency and performance and area scaling for each new technology generation. For further growth as continue to move forward on both "Moore's Law" and "More than Moore", Design and Technology Co-Optimization (DTCO) is getting more important. A lot of technology like Standard cell architecture, 3D IC design flow and so on are introduced to next new technology generation. DTCO examples and challenges will be shared in this presentation.

Takuya Yasui is Director of TSMC Japan Design Center. Received MS degrees in information technology from Hiroshima University in 1993. In the same year, he joined Matsushita Electric Industrial CO., Ltd(Panasonic) and had developed the digital design flow and led ASIC design team. In 2015, he had moved Socionext Inc. which is a joint venture between Panasonic System LSI business and Fujitsu Semiconductor business. In 2020, he joined TSMC and established TSMC Japan Design Center.

Last Updated on: September 8, 2022