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University LSI Design Contest
The University LSI Design Contest has been conceived as a unique program at ASP-DAC. The contest's purpose is to encourage research in LSI design at universities and its realization on a chip by providing opportunities to present and discuss innovative and state-of-the-art design. The scope of the contest covers circuit techniques for (1) Analog / RF / Mixed-Signal Circuits, (2) Digital Signal Processor, (3) Microprocessors, and (4) Custom Application Specific Circuits / Memories, and methodologies for (a) Full-Custom / Cell-Based LSIs, (b) Gate Arrays, and (c) Field Programmable Devices.
This year, the University LSI Design Contest Committee received ten designs from four countries/areas and selected six designs. The selected designs will be discussed in Session 2E on January 17 with short presentations and an interactive poster session. This year, we have an extended poster session to ensure more interaction with the participants. The poster session will start before lunch and continue until the coffee break. Please come and participate in the discussion at a suitable time. The Best Design Award and the Special Feature Award will be presented for two outstanding designs in the opening session. We sincerely acknowledge the other contributions to the contest, too. Our earnest belief is to promote and enhance research and education in LSI design in academic organizations. Please join the University LSI Design Contest and enjoy the stimulating discussions.
- Date: Tuesday, January 17, 2023
- Place:
- Oral Presentation: Miraikan Hall (13:00 ~)
- Poster Presentation: Room Saturn (11:00 ~ 15:10)
- Co-chairs: Mahfuzul Islam (Kyoto University, Japan), Akira Tsuchiya (The University of Shiga Prefecture, Japan)
- University LSI design contest committee
- UDC Session Schedule (html-version)
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| 2E-1 | ViraEye: An Energy-Efficient Stereo Vision Accelerator with Binary Neural Network in 55 nm CMOS |
| 2E-2 | A 1.2nJ/Classification Fully Synthesized All-Digital Asynchronous Wired-Logic Processor Using Quantized Non-linear Function Blocks in 0.18µm CMOS |
| 2E-3 | A Fully Synthesized 13.7μJ/prediction 88% Accuracy CIFAR-10 Single-Chip Data-Reusing Wired-Logic Processor Using Non-Linear Neural Network |
| 2E-4 | A Multimode Hybrid Memristor-CMOS Prototyping Platform Supporting Digital and Analog Projects |
| 2E-5 | A fully synchronous digital LDO with built-in adaptive frequency modulation and implicit dead-zone control |
| 2E-7 | Demonstration of Order Statistics Based Flash ADC in a 65nm Process |