Tutorials

ASP-DAC 2023 offers attendees a set of three-hour intense introductions to specific topics. If you register for tutorials, you have the option to select two out of the seven topics. This year, each tutorial will be provided in a hybrid session format. All the sessions except T4 and T7 are in-person style, and T4 and T7 are through the network. T3 is a session with hands-on training.

  • Date: Monday, January 16, 2023 (9:30 — 17:00)
Room A Room B Room C Room D
9:30 — 12:30 (JST) Tutorial-1
Optimization Problems for Design Automation of Microfluidic Biochips: Scope of Machine Learning
Tutorial-2
Cryogenic Memory Technologies: A Device-to-System Perspective
Tutorial-3
Quantum Annealing for EDA and Its Hands-on Training
Tutorial-4
The Evolution of Functional Verification: SystemVerilog, UVM, and Portable Stimulus
14:00 — 17:00 (JST) Tutorial-5
Design Methods and Computing Paradigms based on Flexible Inorganic Printed Electronics
Tutorial-6
HW/SW Codesign for Reliable In-Memory Computing on Unreliable Technologies: Journey from Beyond-CMOS to Beyond-von Neumann

Tutorial-7
Agile Hardware and Software Co-Design

Tutorial-1: Monday, January 16, 9:30—12:30 (JST) @ Room A

Optimization Problems for Design Automation of Microfluidic Biochips: Scope of Machine Learning

Speakers:
Sudip Roy (Indian Institute of Technology Roorkee)
Shigeru Yamashita (Ritsumeikan University)
Debraj Kundu (Indian Institute of Technology Roorkee)

Abstract:

A microfluidic biochip serves as an integrated mini laboratory, where multiple fluidic operations are performed simultaneously for detection and testing purposes of sample fluids. In contrast to traditional macro systems, biochips provide exceptional resource, cost, and time savings. The device can be used for rapidly screening several biological analytes for a wide range of applications, including disease diagnosis and detection of hazardous biological agents in a system. The global market for biochips, which was previously anticipated to be worth around $13.1 billion in 2020, is now expected to expand to US$25.4 billion by 2026 at a CAGR of 11.7%. Moreover, after a detailed analysis of the financial effects of the COVID-19 pandemic and the economic crisis it caused, the growth of the Lab-on-a-Chip segments is expected to be a revised 12.3% CAGR for the following seven years. To cope with such high demands for biochips, we need to increase the rate of development of microfluidic biochips in parallel. However, the rate of development of such biochips is mainly dependent on the advancements in the corresponding fabrication technologies and design-automation research. This tutorial will cover the analysis of various optimization problems along with the state-of-the-art algorithms, which are developed to solve the challenges for automation of fluidic operations on various kinds of microfluidic biochips. For different biochip platforms like digital and flow-based microfluidic biochips, unique design automation challenges exist. In this tutorial, we treat design automation techniques for various types of digital and flow-based microfluidic biochips including DMFBs (Digital Microfluidic Biochips), FMBs (Flow-based Microfluidic Biochips), MEDAs (Micro-Electrode-Dot-Arrays), PMDs (Programmable Microfluidic Devices) and RMFs (Random Microfluidic Biochips). In the first part of this tutorial, we present the algorithmic motivations and approaches for design automation and sample preparation for all kinds of microfluidic biochips namely DMFBs, FMBs, MEDA-DMFBs, PMDs and RMFs. Sample preparation is an inherent step of many bio-protocols, so an efficient algorithmic approach to solve such a problem is highly desirable. In the second part of the tutorial, the low-level synthesis and optimization problems for PMD based biochips will be discussed. The low-level synthesis for PMD includes loading, washing, and fluid assignment problems, which are unique for PMD based biochips. We will discuss some optimization techniques for loading, washing, and fluid-to-cell assignment in PMDs. In the last part of the tutorial, we will focus on the design automation problems of low-level synthesis of MEDA biochips that includes the methodologies for placement of on-chip fluidic modules and routing of fluids. Due to the intractable nature of these problems, both heuristics and optimization-based methodologies will be discussed. In this tutorial, we will discuss the existing techniques based on machine learning (ML) and reinforcement learning (RL) for various design automation problems of different types of microfluidic biochips.

Biographies:

Sudip Roy is currently an assistant professor in the department of computer science and engineering, IIT Roorkee, India since July 2014. He received the Bachelor of Science degree (Honors) in physics and the Bachelor of Technology degree in computer science and engineering from the University of Calcutta, India, in 2001 and 2004, respectively, and the Master of Science (by research) and Ph.D. degrees in computer science and engineering from the Indian Institute of Technology (IIT) Kharagpur, India, in 2009 and 2014, respectively. He worked as a research associate in the department of computer science and information engineering at National Cheng-Kung University (NCKU), Taiwan in 2014. He was a visiting research scholar in the disaster prevention research institute (DPRI) at Kyoto University, Japan in 2020. He was a JSPS fellow (long-term) in the college of information science and engineering, Ritsumeikan University, Japan during April 2021 to January 2022. He has authored one book, one book chapter, two granted U.S. patents including 27 research articles in international peer-reviewed journals and 43 papers in international peer-reviewed conference proceedings. He is a recipient of the Japan Society for the Promotion of Science (JSPS) Invitational Fellowship in the "Long-Term" category in 2021, the Early-Career Research (ECR) Award from Department of Science and Technology (DST), Govt. of India in 2017, and Microsoft Research India PhD Fellowship Award in 2010. He is a member of IEEE and ACM. His current research interests include computer-aided-design for digital systems, optimization techniques, information and communication technologies (ICT) for disaster risk reduction (DRR).

Shigeru Yamashita is a professor of College of Information Science and Engineering, Ritsumeikan University. He received his B. E., M. E. and Ph.D. degrees in information science from Kyoto University, Kyoto, Japan, in 1993, 1995 and 2001, respectively. In 1995, he joined NTT Communication Science Laboratories, where he engaged in research of computer aided design of digital systems and new type of computer architectures. During 2000 to 2003, he was also a researcher at Quantum Computation and Information, ERATO, Japan Science and Technology Corporation. During 2003 to 2009, he was an associate professor of the Graduate School of Information Science, Nara Institute of Science and Technology. He also served a Visiting Professor at National Institute of Informatics from 2012 to 2017. He received the 2000 IEEE Circuits and Systems Society Transactions on Computer-Aided Design of Integrated Circuits and Systems Best Paper Award, SASIMI 2010 Best Paper Award, 2010 IPSJ Yamashita SIG Research Award, SASIMI 2018 Outstanding Paper Award, Marubun Academic Achievement Award of the Marubun Research Promotion Foundation. He is a senior member of IEEE and IEICE, and a member of ACM and IPSJ.

Debraj Kundu received the B.Tech. degree in computer science and engineering from the Maulana Abul Kalam Azad University of Technology (formerly, known as the West Bengal University of Technology), in 2014 and, the M.Tech. degree in computer science and engineering from the University of Calcutta, Kolkata, India, in 2016. He is currently pursuing the Ph.D. degree from Indian Institute of Technology Roorkee, Roorkee, India. His current research interests include algorithms for computer-aided design of advanced microfluidic biochips. In this domain, he published two research papers in ASPDAC (2019 and 2020), one in DATE (2020), one in DSD (2022), one in TCAD (2022) and one in Integration (2021).



Tutorial-2: Monday, January 16, 9:30—12:30 (JST) @ Room B

Cryogenic Memory Technologies: A Device-to-System Perspective

Speaker:
Ahmedullah Aziz (University of Tennessee Knoxville, USA)

Abstract:

Cryogenic (Cryo) memory technologies have been rapidly garnering interest in recent years due to their immense prospect as potential enablers for multiple exciting technology platforms, including - quantum computing, high performance computing (HPC), and space electronics. The use of ultra-cold (~milli Kelvin) superconducting (SC) qubits are customary in most of the cutting-edge quantum computing systems in existence. The quantum core is accompanied by two other crucial components - a classical control processor and a memory block. Currently, these classical components are kept at room temperature and are interfaced with the quantum substrate through low-density dissipative interconnects. The large thermal gradient resulting therefrom adds extra noise to this sensitive system which already strives to suppress such interferences. To realize a practical quantum computing system (comprising thousands of qubits), it is necessary to keep all relevant components (qubits, control processor, interconnects, and the memory block) at cryogenic environment. Even with the advent of the quantum computing era, ultra-fast and energy-efficient classical computing systems are still in high demand. One of the classical platforms that can achieve this dream combination is superconducting single flux quantum (SFQ) electronics. Interestingly, the capabilities of SFQ processors may not be fully leveraged without pairing it with a suitable cryo memory block. Cryogenic memory is also critically important for space-based applications. A multitude of technologies have already been explored to find suitable candidates for cryogenic data storage. This tutorial provides a comprehensive overview of the existing and emerging variants of cryogenic memory technologies. To ensure an organized discussion, the family of cryogenic memory platforms is categorized into three types: superconducting, non-superconducting, and hybrid. This tutorial covers the device-level key concepts all the way to a system-level overview. The discussion also includes the challenges associated with these technologies and their unique prospects.

Biography:

Ahmedullah Aziz is an Assistant Professor of Electrical Engineering & Computer Science at the University of Tennessee, Knoxville, USA. He earned his Ph.D. in Electrical & Computer Engineering from Purdue University in 2019, an MS degree in Electrical Engineering from the Pennsylvania State University(University Park) in 2016, and a BS degree in Electrical & Electronic Engineering from Bangladesh University of Engineering & Technology (BUET) in 2013. Before beginning his graduate studies, Dr. Aziz worked in the 'Tizen Lab' of the Samsung R&D Institute in Bangladesh as a full-time Engineer. During graduate education, he worked as a Co-Op Engineer (Intern) in the Technology Research division of Global Foundries (Fab 8, NY, USA). He received several awards and accolades for his research, including the 'ACM SIGDA Outstanding Ph.D. Dissertation Award (2021)' from the Association of Computing Machinery, 'EDAA Outstanding Ph.D. Dissertation Award (2020)' from the European Design and Automation Association, 'Outstanding Graduate Student Research Award (2019)' from the College of Engineering, Purdue University, and 'Icon' award from Samsung (2013). He was a co-recipient of two best publication awards (2015, 2016) from the SRC-DARPA STARnet Center and the best project award (2013) from CNSER. He is a technical program committee (TPC) member for multiple flagship conferences (including DAC, ISCAS, GLSVLSI, Nano), a reviewer for several journals from reputed publishers (IEEE, AIP, Elsevier, Frontiers, IOP Science, Springer Nature), and a review panelist for the US Department of Energy (DOE). He serves as an editorial board member for multiple journals including - 'Scientific Reports', and 'Frontiers in Nanotechnology'. Dr. Aziz is an expert in device-circuit co-design and electronic design automation (EDA). His research laid the foundation for physics-based and semi-physical compact modeling of multiple emerging device technologies, including - Mott switches, oxide memristors, ferroelectric transistors, Josephson Junctions, cryotrons, topological memory/switches, and so on. His research portfolio comprises multiple avenues of exploratory nanoelectronics, spanning from device modeling to circuit/array design. In addition, Dr. Aziz has been a trailblazer in cryogenic memory technologies, facilitating critical advancements in quantum computing systems and space electronics.



Tutorial-3: Monday, January 16, 9:30—12:30 (JST) @ Room C

Quantum Annealing for EDA and Its Hands-on Training

Speakers:
Yukihide KOHIRA (University of Aizu)
Takuji HIRAOKA (Fixstars Amplify)
Koji MIZUMATSU (Fixstars)

Abstract:

At present, many quantum annealing machines and Ising machines have been proposed, and several machines have also been put into practical use. However, the software development environment and operation methods of each machine are very different, which makes it difficult for researchers and engineers to use them. The Fixstars Amplify has been developed as a cloud platform to facilitate the development and execution of algorithms for solving combinatorial optimization problems of commercially available quantum annealing machines, Ising machines, mathematical optimization solvers, and gated quantum computers. An overview of its features, several use cases in companies, and examples of researches conducted using the Fixstars Amplify in academia will be introduced in this session. In the second half of the session, a hands-on session on how Fixstars Amplify can be used using the example of combinatorial optimization problem in the manufacturing industry will be conducted.

Biographies:

Yukihide KOHIRA received his B.E., M.E., and D.E. degrees from Tokyo Institute of Technology, Tokyo, Japan, in 2003, 2005, and 2007, respectively. He was a Researcher with the Department of Communications and Integrated Systems, Tokyo Institute of Technology, from 2007 to 2009. In 2009, he joined the School of Computer Science and Engineering, the University of Aizu, where he is currently as a Senior Associate Professor. His research interests include VLSI design automation and combinational algorithms. He is a senior member of IEICE, and a member of IEEE and IPSJ.



Tutorial-4: Monday, January 16, 9:30—12:30 (JST) @ Room D

The Evolution of Functional Verification: SystemVerilog, UVM, and Portable Stimulus

Speaker:
Tom Fitzpatric (Siemens Digital Industries Software)

Abstract:

We all know that the size and complexity of electronic chips and systems have increased dramatically over the past decade or so. Unfortunately, as designs get more complex the difficulty of verifying their functionality increases at an even more dramatic rate. To have any hope of ensuring that designs function as they're intended, the functional verification landscape has undergone a corresponding evolution to include more powerful algorithms, techniques, and tools. Test writers have moved from signal-level directed tests to fully-automated self-checking test environments that can execute orders of magnitude more tests to exercise and verify the vastly growing functionality of today's (and tomorrow's) designs. This technical tutorial will take the audience on a guided tour through the most important advances in functional verification in the last twenty years. Beginning with the standardization of constrained-random stimulus, functional coverage, and other key features in SystemVerilog, we will investigate the advantages of including automation as part of a verification environment and the accompanying techniques required to maximize productivity by abstracting verification to the level of transactions. This will lead to a discussion of the Universal Verification Methodology, the first standard to allow and encourage the development of modular, reusable, transaction-level verification components. We will explore all aspects of the UVM and see the advantages it provides in separating the creation of transaction-level tests written as UVM sequences from the specification of a flexible, reusable component-based test environment. We will then examine the limitations of UVM for developing a software-driven SoC verification environment and introduce the new Portable Test and Stimulus Standard (PSS) that allows the creation of automated constrained-random scenario-level tests that can be used to generate test implementations targeted to both UVM environments and to C-based tests to run on SoC platforms in simulation, emulation, or silicon.

Biography:

Tom Fitzpatrick is a Strategic Verification Architect at Siemens Digital Industries Software (Siemens EDA) where he works on developing advanced verification methodologies, languages, and standards. He has been a significant contributor to several industry standards that have dramatically improved the functional verification landscape over the last 25 years, including Verilog 1364, SystemVerilog 1800, and UVM 1800.2. He is a founding member and current Vice-Chair of the Accellera Portable Stimulus Working Group and currently serves as the Chair of the IEEE 1800 and Accellera UVM-AMS Working Groups. In 2019, he received the Accellera Technical Excellence Award in recognition of his many contributions to that organization over the years, and he is also the recipient of the 2022 Ron Waxman Meritorious Service Award from the IEEE Design Automation Standards Committee. He has published multiple articles and technical papers on a wide variety of functional verification topics and has produced some of the most popular and successful video training courses on Siemens' Verification Academy website. Tom is a long-time member of the DVCon US Steering Committee and a member of the Design Automation Conference Executive Committee. Tom holds Master's and Bachelor's degrees in Electrical Engineering and Computer Science from MIT, is an avid golfer, and is a huge Boston Red Sox and New England Patriots fan. He and his wife, Dee, to whom he has been married for 26 years, have two children who once swore that they would never become engineers. His son, David, is a Ph.D. student in Aerospace Engineering at the University of Colorado, Boulder, and his daughter, Megan, is an Environmental Engineering major at Villanova University.



Tutorial-5: Monday, January 16, 14:00—17:00 (JST) @ Room A

Design Methods and Computing Paradigms based on Flexible Inorganic Printed Electronics

Speaker:
Mehdi B. Tahoori (Karlsruhe Institute of Technology)

Abstract:

Flexible electronics is an emerging and fast-growing field which can be used in many demanding and emerging application domains such as wearables, smart sensors, and Internet of Things (IoT). Unlike traditional computing and electronics domain which is mostly driven by performance characteristics, flexible electronics based on additive manufacturing processes are mainly associated with low fabrication costs (as they are used even in consumer market) and low energy consumption (as they could be used in energy-harvested systems). Printed electronics offer certain technological advantages over their silicon based counterparts, like mechanical flexibility, low process temperatures, maskless and additive manufacturing possibilities. However, it is essential that the printed devices operate at low supply voltages. Electrolyte gated transistors (EGTs) using solution-processed inorganic materials which are fully printed using inkject printers at low temperatures are very promising to provide such solutions. In this tutorial, I discuss the technology, process, modeling, fabrication, design (automation), computing paradigms and security aspects of circuits based on additive printed technologies.

Biography:

Mehdi Tahoori is a full professor and Chair of Dependable Nano-Computing (CDNC) at the Institute of Computer Science & Engineering (ITEC), Department of Computer Science, Karlsruhe Institute of Technology (KIT), Germany. He received his PhD and M.S. degrees in Electrical Engineering from Stanford University in 2003 and 2002, respectively, and a B.S. in Computer Engineering from Sharif University of Technology in Iran, in 2000. In 2003, he joined the Electrical and Computer Engineering Department at the Northeastern University as an assistant professor where he promoted to the rank of associate professor with tenure in 2009. From August to December 2015, he was a visiting professor at VLSI Design and Education Center (VDEC), University of Tokyo, Japan. From 2002 to 2003, he was a Research Scientist with Fujitsu Laboratories of America, Sunnyvale, CA, in the area of advanced computer-aided research, engaged in reliability issues in deep-submicrometer mixed-signal very large-scale integration (VLSI) designs. He is currently the deputy editor-in-chief of IEEE Design and Test Magazine. He was the editor-in-chief of Microelectronic Reliability journal. He was the program chair of VLSI Test Symposium in (VTS) in 2021and 2018, and General Chair of European Test Symposium (ETS) in 2019. Prof. Tahoori was a recipient of the US National Science Foundation Early Faculty Development (CAREER) Award in 2008. He has received a number of best paper nominations and awards at various conferences and journals. He is a fellow of the IEEE and a recipient of European Research Council (ERC) Advanced Grant on Printed Computing. He is currently the chair of IEEE European Test Technologies Technical Council (eTTTC).



Tutorial-6: Monday, January 16, 14:00—17:00 (JST) @ Room B

HW/SW Codesign for Reliable In-Memory Computing on Unreliable Technologies: Journey from Beyond-CMOS to Beyond-von Neumann

Speaker:
Hussam Amrouch (University of Stuttgart)

Abstract:

Breakthroughs in deep learning continuously fuel innovations that profoundly improve our daily life. However, DNNs largely overwhelm conventional computing systems because they are severely bottlenecked by the data movement between processing units and memory. As a result, novel and intelligent computing systems become more and more inevitable to enhance or even replace the current von-Neumann architecture, which has remained unchanged since decades. This tutorial provides a comprehensive overview on the major shortcomings of modern architectures and the ever-increasing necessity for novel designs that fundamentally reduce memory latency and energy through enabling data processing inside the memory itself. The tutorial will also discuss in detail the great promise of recent emerging beyond-CMOS devices like Ferroelectric Field-Effect Transistor (FeFET). It will bridge the gap between the latest innovations in the underlying technology and the recent breakthroughs in computer architectures. It will demonstrate how HW/SW codesign is a key to realize efficient and reliable in-memory computing.

Biography:

Hussam Amrouch is a Jun.-Professor heading the Chair of Semiconductor Test and Reliability (STAR) within the Computer Science, Electrical Engineering Faculty at the University of Stuttgart as well as a Research Group Leader at the Karlsruhe Institute of Technology (KIT), Germany. He currently serves as Editor at the Nature Scientific Reports Journal. He received his Ph.D. degree with the highest distinction (Summa cum laude) from KIT in 2015. He has around 190 publications (including 76 journals including one in Nature SR) in multidisciplinary research areas across the entire computing stack, starting from semiconductor physics to circuit design all the way up to computer-aided design and computer architecture. His main research interests are AI processor design, emerging beyond-von-Neumann architectures, design for reliability from device physics to systems, machine learning for CAD, HW security, and emerging technologies with a special focus on ferroelectric devices. He has served in the technical program committees of many major EDA conferences such as DAC, ASP-DAC, ICCAD, etc. and as a reviewer in many top journals like Nature Electronics, T-ED, TCAS-I, TVLSI, TCAD, TC, etc. He holds eight HiPEAC Paper Awards and three best paper nominations at top EDA conferences: DAC'16, DAC'17 and DATE'17 for his work on reliability. He has given around 30 invited talks in international universities, and major EDA companies like Synopsys and Silvaco as well as more than 10 tutorials in several top EDA conferences such as DAC, ICCAD, DATE, etc. His research in reliability have been funded by the German Research Foundation (DFG), Advantest Corporation, and the U.S. Office of Naval Research (ONR).



Tutorial-7: Monday, January 16, 14:00—17:00 (JST) @ Room D

Agile Hardware and Software Co-Design

Speakers:
Yun Eric Liang (Peking University)
Cheng Zhuo (Zhejiang University)
Wei Zhang (Hong Kong University of Science and Technology)

Abstract:

As Moore's law is approaching to the end, designing specialized hardware along with the software that map the applications onto the specialized hardware is a promising solution. The hardware design determines the peak performance, while the software is also important as it determines the actual performance. Hardware/software (HW/SW) co-design can optimize the hardware and software in concert and improve overall performance. However, the current flow designs hardware and software in isolation. More importantly, both hardware and software are difficult to design and optimize due to the low-level programming and huge design space.

Biographies:

Yun Eric Liang is currently an Associate Professor (with tenure) in the School of Integrated Circuit at Peking University and a member of Center for Energy-efficient Computing and Applications (CECA). His research interest is at the hardware-software interface with work spanning electronic design automation (EDA), hardware and software co-design, and computer architecture. He has authored over 100 scientific publications in the leading international journals and conferences. My research has been recognized with two Best Paper Awards (FCCM 2011 and ICCAD 2017), six Best Paper Award Nominations (PPoPP 2019, DAC 2017, ASPDAC 2016, DAC 2012, FPT 2011, CODES+ISSS 2008). He currently serves as Associate Editor of the ACM Transactions on Embedded Computing Systems (TECS) and ACM Transactions on Reconfigurable Technology and Systems (TRETS). He is the program chair of International Conference on Field Programmable Technology (FPT) 2022 and International Conference on Application-specific Systems, Architecture and Processors (ASAP) 2019 and the subcommittee chair of Asia South Pacific Design Automation Conference (ASPDAC) 2014. He also serves in the program committees in the premier conferences including DAC, ICCAD, DATE, ASPDAC, FPGA, FCCM, HPCA, MICRO, PACT, CGO, ICS, CC, CASES, LCTES, ASAP, and ICCD.

Cheng Zhuo received the Ph.D. degree in computer science engineering from the University of Michigan, Ann Arbor, MI, USA, in 2010. After 6 years in industry, he is currently a professor with the College of Information Science Electronic Engineering, Zhejiang University, with research focus on software-hardware co-design, hardware acceleration, and power/signal integrity. Dr. Zhuo has published over 150 technical publications and received multiple best paper award nominations including DAC and ICCAD. Dr. Zhuo has served on the organization and technical program committees of over 30 international conferences and serves as Associate Editor for IEEE TCAD, ACM TODAES, and Elsevier Integration. He co-founded ACM/SIGDA East China Chapter and serves as the founding chair. He is a senior member of IEEE and a Fellow of IET.

Wei Zhang is currently an Associate Professor with the Department of Electronic and Computer Engineering, the Hong Kong University of Science and Technology (HKUST). She was an Assistant Professor with the School of Computer Engineering, Nanyang Technological University, Singapore, from 2010 to 2013. She joined HKUST in 2013 and established Reconfigurable Computing Systems Lab. She has authored over 100 technical papers in referred international journals and conferences and authored three book chapters. Her team has won the best paper award in ISVLSI 2009 and ICCAD 2017.Prof. Zhang currently serves in several editorial boards as Associate Editor including ACM Transactions on Reconfigurable Technology and Systems (TRETS), IEEE Transaction on Very Large Scale Integration (TVLSI) Systems, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), ACM Transactions on Embedded Computing Systems (TECS), and ACM Journal on Emerging Technologies in Computing Systems (JETC). She also serves on many organization committees and technical program committees, such as DAC, ICCAD, CASES, FPGA, FCCM, etc.



Last Updated on: November 25, 2022