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ASP-DAC 2006 Archives
6A-1
| Title | Mathematically Assisted Adaptive Body Bias (ABB) for Temperature Compensation in Gigascale LSI Systems |
| Author | Sanjay V Kumar, Chris H Kim, *Sachin S Sapatnekar (University of Minnesota, United States) |
| Abstract | Process variations and temperature variations can cause the frequency and leakage of the chip to vary significantly from their expected values, thereby decreasing the yield. Adaptive Body Bias (ABB) can be used to pull back the chip to the nominal operational region. We propose the use of this technique to counter temperature variations along with process variations. We present a CAD perspective for achieving process and temperature compensation using bidirectional ABB. Mathematical models are used to determine the exact amount of body bias required to optimize the delay and leakage, and an algorithmic flow that can be adopted for gigascale LSI systems is provided. |
| Slides (pdf file) | 6A-1 |
6A-2
| Title | Analysis and Optimization of Gate Leakage Current of Power Gating Circuits |
| Author | *Hyung-Ock Kim, Youngsoo Shin (Dept. of Electrical Engineering, KAIST, Republic of Korea) |
| Abstract | Power gating is widely accepted as an efficient way to suppress subthreshold leakage current. Yet, it suffers from gate leakage current, which grows very fast with scaling down of gate oxide. We try to understand the sources of leakage current in power gating circuits and show that input MOSFETs play a crucial role in determining total gate leakage current. It is also shown that the choice of a current switch in terms of polarity, threshold voltage, and size has a significant impact on total leakage current. From the observation of the importance of input MOSFETs, we propose the power optimization of power gating circuits through input control. |
| Slides (pdf file) | 6A-2 |
6A-3
| Title | Delay Modeling and Static Timing Analysis for MTCMOS Circuits |
| Author | *Naoaki Ohkubo, Kimiyoshi Usami (Graduate School of Engineering, Shibaura Institute of Technology, Japan) |
| Abstract | One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In this paper, we propose a delay modeling and static timing analysis (STA) methodology targeting at MTCMOS circuits. In the proposed method, we prepare a delay look-up table (LUT) consisting of the input slew, the output load capacitance, the virtual ground length, and a power-switch size. Using this LUT, we compute a circuit delay for each logic cell by applying the linear interpolation. Experimental results show that the proposed methodology enables to estimate the critical path delay in a good accuracy. |
| Slides (pdf file) | 6A-3 |
6A-4
| Title | Switching-Activity Driven Gate Sizing and Vth Assignment for Low Power Design |
| Author | Yu-Hui Huang, *Po-Yuan Chen, TingTing Hwang (National Tsing Hua University, Taiwan) |
| Abstract | Power consumption has gained much saliency in circuit design recently. One design problem is modelled as "Under a timing constraint, to minimize power as much as possible". Previous research regarding this problem focused on either minimizing dynamic power by gate sizing, or reducing leakage power by dual threshold voltage assignment on non-critical path. However, given a timing constraint, an optimization algorithm must be able to utilize gate sizing and threshold-voltage assignment interchangeably, in order to minimize total power consumption including dynamic and leakage power in active mode and leakage power in idle mode. We find that switching-activity of a gate plays an important role in making decision as to choosing gate sizing or threshold-voltage assignment for performance improvement. For high switching-activity gates, threshold-voltage assignment should be used while for low switching-activity gates, gate sizing should be utilized. We develop an algorithm to perform gate sizing and threshold-voltage assignment simultaneously taking switching activity into consideration. The results show that under the same timing constraint, our circuits have 16.26%, and 18.53%, improvement of total power as compared to the original circuits for the cases where the percentage of active time are 100%, and 50%, respectively. |
| Slides (pdf file) | 6A-4 |
6A-5
| Title | Power Driven Placement with Layout Aware Supply Voltage Assignment for Voltage Island Generation in Dual-Vdd Designs |
| Author | *Bin Liu, Yici Cai, Qiang Zhou, Xianlong Hong (Tsinghua University, China) |
| Abstract | In this paper we propose a method for standard cell placement with support for dual supply voltages, aiming to reduce total power under timing constraints and to implement voltage islands with minimal overheads. The method begins with timing and power driven coarse placement, followed by a few iterations between voltage assignment and placement refinement to generate voltage islands. Several techniques, including timing and power driven net weighting, seed growth based voltage assignment, and soft clustering strategy for placement refinements are employed in our implementation. Experimental results on a set of MCNC benchmarks show that our approach is able to produce feasible placement for dual-Vdd designs and significantly reduce total power with a wirelength increase within 14% compared to a power and timing driven placer without voltage islands. |
| Slides (pdf file) | 6A-5 |