Title | A H.264/MPEG-2 Dual Mode Video Decoder Chip Supporting Temporal/Spatial Scalable Video |
Author | *Cheng-An Chien, Yao-Chang Yang, Hsiu-Cheng Chang, Jia-Wei Chen, Cheng-Yen Chang, Jiun-In Guo, Jinn-Shyan Wang (National Chung Cheng Univ., Taiwan), Ching-Hwa Cheng (Feng Chia Univ., Taiwan) |
Page | pp. 73 - 74 |
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Title | A Gate-level Pipelined 2.97GHz Self Synchronous FPGA in 65nm CMOS |
Author | *Benjamin Devlin, Makoto Ikeda, Kunihiro Asada (Univ. of Tokyo, Japan) |
Page | pp. 75 - 76 |
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Title | A 4.32 mm2 170mW LDPC Decoder in 0.13µm CMOS for WiMax/Wi-Fi Applications |
Author | *Dan Bao, Chuan Wu, Yan Ying, Yun Chen, Xiao Yang Zeng (Fudan Univ., China) |
Page | pp. 77 - 78 |
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Title | All-Digital PMOS and NMOS Process Variability Monitor Utilizing Buffer Ring with Pulse Counter |
Author | *Jaehyun Jeong, Tetsuya Iizuka, Toru Nakura, Makoto Ikeda, Kunihiro Asada (Univ. of Tokyo, Japan) |
Page | pp. 79 - 80 |
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Title | Jitter Amplifier for Oscillator-Based True Random Number Generator |
Author | *Takehiko Amaki, Masanori Hashimoto, Takao Onoye (Osaka Univ., Japan) |
Page | pp. 81 - 82 |
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Title | A 65nm Flip-Flop Array to Measure Soft Error Resiliency against High-Energy Neutron and Alpha Particles |
Author | *Jun Furuta (Kyoto Univ., Japan), Chikara Hamanaka, Kazutoshi Kobayashi (Kyoto Inst. of Tech., Japan), Hidetoshi Onodera (Kyoto Univ., Japan) |
Page | pp. 83 - 84 |
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Title | Dual-Phase Pipeline Circuit Design Automation with a Built-in Performance Adjusting Mechanism |
Author | Yu-Tzu Tsai, Cheng-Chih Tsai (Feng Chia Univ., Taiwan), *Cheng-An Chien (National Chung Cheng Univ., Taiwan), Ching-Hwa Cheng (Feng Chia Univ., Taiwan), Jiun-In Guo (National Chung Cheng Univ., Taiwan) |
Page | pp. 85 - 86 |
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Title | Geyser-2: The Second Prototype CPU with Fine-grained Run-time Power Gating |
Author | *Lei Zhao, Daisuke Ikebuchi, Yoshiki Saito, Masahiro Kamata, Naomi Seki, Yu Kojima, Hideharu Amano (Keio Univ., Japan), Satoshi Koyama, Tatsunori Hashida, Yusuke Umahashi, Daiki Masuda, Kimiyoshi Usami (Shibaura Inst. of Tech., Japan), Kazuki Kimura, Mitaro Namiki (Tokyo Univ. of Agri. and Tech., Japan), Seidai Takeda, Hiroshi Nakamura (Univ. of Tokyo, Japan), Masaaki Kondo (Univ. of Electro-Communications, Japan) |
Page | pp. 87 - 88 |
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Title | An Implementation of an Asychronous FPGA Based on LEDR/Four-Phase-Dual-Rail Hybrid Architecture |
Author | *Yoshiya Komatsu, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ., Japan) |
Page | pp. 89 - 90 |
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Title | Design and Chip Implementation of a Heterogeneous Multi-core DSP |
Author | *Shuming Chen, Xiaowen Chen, Yi Xu, Jianghua Wan, Jianzhuang Lu, Xiangyuan Liu, Shenggang Chen (National Univ. of Defense Tech., China) |
Page | pp. 91 - 92 |
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Title | A Low-Power Management Technique for High-Performance Domino Circuits |
Author | Yu-Tzu Tsai, Cheng-Chih Tsai (Feng Chia Univ., Taiwan), *Cheng-An Chien (National Chung Cheng Univ., Taiwan), Ching-Hwa Cheng (Feng Chia Univ., Taiwan), Jiun-In Guo (National Chung Cheng Univ., Taiwan) |
Page | pp. 93 - 94 |
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Title | Design and Evaluation of Variable Stages Pipeline Processor Chip |
Author | *Tomoyuki Nakabayashi, Takahiro Sasaki, Kazuhiko Ohno, Toshio Kondo (Mie Univ., Japan) |
Page | pp. 95 - 96 |
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Title | TurboVG: A HW/SW Co-Designed Multi-Core OpenVG Accelerator for Vector Graphics Applications with Embedded Power Profiler |
Author | *Shuo-Hung Chen, Hsiao-Mei Lin, Ching-Chou Hsieh, Chih-Tsun Huang, Jing-Jia Liou, Yeh-Ching Chung (National Tsing Hua Univ., Taiwan) |
Page | pp. 97 - 98 |
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Title | Design and Implementation of a High Performance Closed-Loop MIMO Communications with Ultra Low Complexity Handset |
Author | *Yu-Han Yuan, Wei-Ming Chen, Hsi-Pin Ma (National Tsing Hua Univ., Taiwan) |
Page | pp. 99 - 100 |
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Title | A 58-63.6GHz Quadrature PLL Frequency Synthesizer Using Dual-Injection Technique |
Author | *Ahmed Musa, Rui Murakami, Takahiro Sato, Win Chiavipas, Kenichi Okada, Akira Matsuzawa (Tokyo Inst. of Tech., Japan) |
Page | pp. 101 - 102 |
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Title | An Ultra-low-voltage LC-VCO with a Frequency Extension Circuit for Future 0.5-V Clock Generation |
Author | *Wei Deng, Kenichi Okada, Akira Matsuzawa (Tokyo Inst. of Tech., Japan) |
Page | pp. 103 - 104 |
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Title | A 32Gbps Low Propagation Delay 4x4 Switch IC for Feedback-Based System in 0.13µm CMOS Technology |
Author | Yu-Hao Hsu, Yang-Syu Lin, Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu, Fan-Ta Chen, Min-Sheng Kao, *Wei-Chih Lai, YarSun Hsu (National Tsing Hua Univ., Taiwan) |
Page | pp. 105 - 106 |
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Title | A Fully Integrated Shock Wave Transmitter with an On-Chip Dipole Antenna for Pulse Beam-Formability in 0.18-μm CMOS |
Author | *Nguyen Ngoc Mai Khanh, Masahiro Sasaki, Kunihiro Asada (Univ. of Tokyo, Japan) |
Page | pp. 107 - 108 |
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Title | An On-Chip Characterizing System for Within-Die Delay Variation Measurement of Individual Standard Cells in 65-nm CMOS |
Author | *Xin Zhang, Koichi Ishida, Makoto Takamiya, Takayasu Sakurai (Univ. of Tokyo, Japan) |
Page | pp. 109 - 110 |
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Title | Robust and Efficient Baseband Receiver Design for MB-OFDM UWB System |
Author | Wen Fan, *Chiu-Sing Choy (Chinese Univ. of Hong Kong, Hong Kong) |
Page | pp. 111 - 112 |
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Title | A 95-nA, 523ppm/°C, 0.6-µW CMOS Current Reference Circuit with Subthreshold MOS Resistor Ladder |
Author | *Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa (Kobe Univ., Japan) |
Page | pp. 113 - 114 |
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Title | A 80-400 MHz 74 dB-DR Gm-C Low-Pass Filter With a Unique Auto-Tuning System |
Author | *Ting Gao, Wei Li, Ning Li, Junyan Ren (Fudan Univ., China) |
Page | pp. 115 - 116 |
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Title | An Adaptively Biased Low-Dropout Regulator with Transient Enhancement |
Author | *Chenchang Zhan, Wing-Hung Ki (Hong Kong Univ. of Science and Tech., Hong Kong) |
Page | pp. 117 - 118 |
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Title | A Low-Power Triple-Mode Sigma-Delta DAC for Reconfigurable (WCDMA/TD-SCDMA/GSM) Transmitters |
Author | *Dong Qiu, Ting Yi, Zhiliang Hong (Fudan Univ., China) |
Page | pp. 119 - 120 |
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Title | A Simple Non-coherent Solution to the UWB-IR Communication |
Author | *Mohiuddin Hafiz, Nobuo Sasaki, Kentaro Kimoto, Takamaro Kikkawa (Hiroshima Univ., Japan) |
Page | pp. 121 - 122 |
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