The 16th Asia and South Pacific Design Automation Conference
Technical Program

Remark: The presenter of each paper is marked with "*".

Technical Program: SIMPLE version DETAILED version with abstract One Page (Not Separated) version

Author Index: HERE

Session Schedule

Wednesday, January 26, 2011

Room 411+412	Room 413	Room 414+415	Room 416+417
1K (Room 503) Opening and Keynote Session I 8:30 - 10:00
1A Analog, Mixed-Signal & RF Verification, Abstraction and Analysis 10:20 - 12:20	1B Emerging Memories and System Applications 10:20 - 12:20	1C Advances in Model Order Reduction and Extraction Techniques 10:20 - 12:20	1D University LSI Design Contest 10:20 - 12:20
2A Scheduling Techniques for Embedded Systems 13:40 - 15:40	2B Memory Architecture and Buffer Optimization 13:40 - 15:40	2C Modeling for Signal and Power Integrity 13:40 - 15:40	2D Special Session: Emerging Memory Technologies and Its Implication on Circuit Design and Architectures 13:40 - 15:40
3A High-Level Embedded Systems Design Techniques 16:00 - 18:00	3B Timing, Power, and Thermal Issues 16:00 - 18:00	3C Special Session: Post-Silicon Techniques to Counter Process and Electrical Parameter Variability 16:00 - 18:00	3D Special Session: Recent Advances in Verification and Debug 16:00 - 18:00

Thursday, January 27, 2011

Room 411+412	Room 413	Room 414+415	Room 416+417
2K (Room 503) Keynote Session II 9:00 - 10:00
4A Design Automation for Emerging Technologies 10:20 - 12:20	4B Novel Network-on-Chip Architecture Design 10:20 - 12:20	4C Architecture Design and Reliability 10:20 - 12:20	4D Special Session: Advanced Patterning and DFM for Nanolithography beyond 22nm 10:20 - 12:20
5A System-Level Simulation 13:40 - 15:40	5B Resilient and Thermal-Aware NoC Design 13:40 - 15:40	5C High-Level and Logic Synthesis 13:40 - 15:40	5D Designers' Forum: C-P-B Co-design/Co-verification Technology for DDR3 1.6G in Consumer Products 13:40 - 15:40
6A Design Validation Techniques 16:00 - 18:00	6B Clock Network Design 16:00 - 18:00	6C Advances in Routing 16:00 - 18:00	6D Designers' Forum: Emerging Technologies for Wellness Applications 16:00 - 18:00

Friday, January 28, 2011

Room 411+412	Room 413	Room 414+415	Room 416+417
3K (Room 503) Keynote Session III 9:00 - 10:00
7A System Level Analysis and Optimization 10:20 - 12:20	7B NBTI and Power Gating 10:20 - 12:20	7C Physical Design for Yield 10:20 - 12:20	7D Special Session: Virtualization, Programming, and Energy-Efficiency Design Issues of Embedded Systems 10:20 - 12:20
8A Modeling and Design for Variability 13:40 - 15:40	8B Test for Reliability and Yield 13:40 - 15:40	8C System-Level Power Optimization 13:40 - 15:40	8D Designers' Forum: State-of-The-Art SoCs and Design Methodologies 13:40 - 15:40
9A Printability and Mask Optimization 16:00 - 18:00	9B Emerging Solutions in Scan Testing 16:00 - 18:00	9C Clock and Package 16:00 - 18:00	9D Designers' Forum: Advanced Packaging and 3D Technologies 16:00 - 18:00