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The 16th Asia and South Pacific Design Automation Conference
Technical Program

Remark: The presenter of each paper is marked with "*".
Technical Program:   SIMPLE version   DETAILED version with abstract
Author Index:   HERE

Session Schedule


Wednesday, January 26, 2011

Room 411+412Room 413Room 414+415Room 416+417
1K  (Room 503)
Opening and Keynote Session I

8:30 - 10:00
1A  Analog, Mixed-Signal & RF Verification, Abstraction and Analysis
10:20 - 12:20
1B  Emerging Memories and System Applications
10:20 - 12:20
1C  Advances in Model Order Reduction and Extraction Techniques
10:20 - 12:20
1D  University LSI Design Contest
10:20 - 12:20
2A  Scheduling Techniques for Embedded Systems
13:40 - 15:40
2B  Memory Architecture and Buffer Optimization
13:40 - 15:40
2C  Modeling for Signal and Power Integrity
13:40 - 15:40
2D  Special Session: Emerging Memory Technologies and Its Implication on Circuit Design and Architectures
13:40 - 15:40
3A  High-Level Embedded Systems Design Techniques
16:00 - 18:00
3B  Timing, Power, and Thermal Issues
16:00 - 18:00
3C  Special Session: Post-Silicon Techniques to Counter Process and Electrical Parameter Variability
16:00 - 18:00
3D  Special Session: Recent Advances in Verification and Debug
16:00 - 18:00



Thursday, January 27, 2011

Room 411+412Room 413Room 414+415Room 416+417
2K  (Room 503)
Keynote Session II

9:00 - 10:00
4A  Design Automation for Emerging Technologies
10:20 - 12:20
4B  Novel Network-on-Chip Architecture Design
10:20 - 12:20
4C  Architecture Design and Reliability
10:20 - 12:20
4D  Special Session: Advanced Patterning and DFM for Nanolithography beyond 22nm
10:20 - 12:20
5A  System-Level Simulation
13:40 - 15:40
5B  Resilient and Thermal-Aware NoC Design
13:40 - 15:40
5C  High-Level and Logic Synthesis
13:40 - 15:40
5D  Designers' Forum: C-P-B Co-design/Co-verification Technology for DDR3 1.6G in Consumer Products
13:40 - 15:40
6A  Design Validation Techniques
16:00 - 18:00
6B  Clock Network Design
16:00 - 18:00
6C  Advances in Routing
16:00 - 18:00
6D  Designers' Forum: Emerging Technologies for Wellness Applications
16:00 - 18:00



Friday, January 28, 2011

Room 411+412Room 413Room 414+415Room 416+417
3K  (Room 503)
Keynote Session III

9:00 - 10:00
7A  System Level Analysis and Optimization
10:20 - 12:20
7B  NBTI and Power Gating
10:20 - 12:20
7C  Physical Design for Yield
10:20 - 12:20
7D  Special Session: Virtualization, Programming, and Energy-Efficiency Design Issues of Embedded Systems
10:20 - 12:20
8A  Modeling and Design for Variability
13:40 - 15:40
8B  Test for Reliability and Yield
13:40 - 15:40
8C  System-Level Power Optimization
13:40 - 15:40
8D  Designers' Forum: State-of-The-Art SoCs and Design Methodologies
13:40 - 15:40
9A  Printability and Mask Optimization
16:00 - 18:00
9B  Emerging Solutions in Scan Testing
16:00 - 18:00
9C  Clock and Package
16:00 - 18:00
9D  Designers' Forum: Advanced Packaging and 3D Technologies
16:00 - 18:00



List of Papers

Remark: The presenter of each paper is marked with "*".

Wednesday, January 26, 2011

Session 1K  Opening and Keynote Session I
Time: 8:30 - 10:00 Wednesday, January 26, 2011
Location: Room 503
Chair: Kunihiro Asada (Univ. of Tokyo, Japan)

1K-1 (Time: 9:00 - 10:00)
Title(Keynote Address) Non-Volatile Memory and Normally-Off Computing
AuthorTakayuki Kawahara (Hitachi, Japan)
Detailed information (abstract, keywords, etc)
Slides


Session 1A  Analog, Mixed-Signal & RF Verification, Abstraction and Analysis
Time: 10:20 - 12:20 Wednesday, January 26, 2011
Location: Room 411+412
Chairs: Eric Keiter (Sandia National Labs, U.S.A.), Chin-Fong Chiu (National Chip Implementation Center, Taiwan)

1A-1 (Time: 10:20 - 10:50)
TitleAnalog Circuit Verification by Statistical Model Checking
Author*Ying-Chih Wang, Anvesh Komuravelli, Paolo Zuliani, Edmund M. Clarke (Carnegie Mellon Univ., U.S.A.)
Pagepp. 1 - 6
Detailed information (abstract, keywords, etc)
Slides

1A-2 (Time: 10:50 - 11:20)
TitleFSM Model Abstraction for Analog/Mixed-Signal Circuits by Learning from I/O Trajectories
Author*Chenjie Gu, Jaijeet Roychowdhury (Univ. of California, Berkeley, U.S.A.)
Pagepp. 7 - 12
Detailed information (abstract, keywords, etc)

1A-3 (Time: 11:20 - 11:50)
TitleA Structured Parallel Periodic Arnoldi Shooting Algorithm for RF-PSS Analysis based on GPU Platforms
AuthorXue-Xin Liu (Univ. of California, Riverside, U.S.A.), Hao Yu (Nanyang Technological Univ., Singapore), Jacob Relles, *Sheldon X.-D. Tan (Univ. of California, Riverside, U.S.A.)
Pagepp. 13 - 18
Detailed information (abstract, keywords, etc)

1A-4 (Time: 11:50 - 12:20)
TitleHierarchical Exact Symbolic Analysis of Large Analog Integrated Circuits By Symbolic Stamps
Author*Hui Xu, Guoyong Shi, Xiaopeng Li (Shanghai Jiao Tong Univ., China)
Pagepp. 19 - 24
Detailed information (abstract, keywords, etc)
Slides


Session 1B  Emerging Memories and System Applications
Time: 10:20 - 12:20 Wednesday, January 26, 2011
Location: Room 413
Chairs: Mehdi Tahoori (Karlsruhe Inst. of Tech., Germany), Chun-Ming Huang (National Chip Implementation Center, Taiwan)

1B-1 (Time: 10:20 - 10:50)
TitleGeometry Variations Analysis of TiO2 Thin-Film and Spintronic Memristors
Author*Miao Hu, Hai Li (Polytechnic Institute of New York Univ., U.S.A.), Yiran Chen (Univ. of Pittsburgh, U.S.A.), Xiaobin Wang (Seagate Technology, U.S.A.), Robinson Pino (AFRL/RITC, U.S.A.)
Pagepp. 25 - 30
Detailed information (abstract, keywords, etc)
Slides

1B-2 (Time: 10:50 - 11:20)
TitleAdaMS: Adaptive MLC/SLC Phase-Change Memory Design for File Storage
Author*Xiangyu Dong, Yuan Xie (Pennsylvania State Univ., U.S.A.)
Pagepp. 31 - 36
Detailed information (abstract, keywords, etc)
Slides

1B-3 (Time: 11:20 - 11:50)
TitleSystem Accuracy Estimation of SRAM-based Device Authentication
AuthorJoonsoo Kim, Joonsoo Lee, *Jacob A. Abraham (Univ. of Texas, Austin, U.S.A.)
Pagepp. 37 - 42
Detailed information (abstract, keywords, etc)

1B-4 (Time: 11:50 - 12:20)
TitleOn-Chip Hybrid Power Supply System for Wireless Sensor Nodes
Author*Wulong Liu, Yu Wang, Wei Liu, Yuchun Ma (Tsinghua Univ., China), Yuan Xie (Pennsylvania State Univ., U.S.A.), Huazhong Yang (Tsinghua Univ., China)
Pagepp. 43 - 48
Detailed information (abstract, keywords, etc)
Slides


Session 1C  Advances in Model Order Reduction and Extraction Techniques
Time: 10:20 - 12:20 Wednesday, January 26, 2011
Location: Room 414+415
Chairs: Sheldon X.-D. Tan (Univ. of California, Riverside, U.S.A.), Genichi Tanaka (Renesas, Japan)

1C-1 (Time: 10:20 - 10:50)
TitleA Moment-Matching Scheme for the Passivity-Preserving Model Order Reduction of Indefinite Descriptor Systems with Possible Polynomial Parts
Author*Zheng Zhang (Massachusetts Inst. of Tech., U.S.A.), Qing Wang, Ngai Wong (Univ. of Hong Kong, Hong Kong), Luca Daniel (Massachusetts Inst. of Tech., U.S.A.)
Pagepp. 49 - 54
Detailed information (abstract, keywords, etc)
Slides

1C-2 (Time: 10:50 - 11:20)
TitleBalanced Truncation for Time-Delay Systems Via Approximate Gramians
Author*Xiang Wang, Qing Wang, Zheng Zhang, Quan Chen, Ngai Wong (Univ. of Hong Kong, Hong Kong)
Pagepp. 55 - 60
Detailed information (abstract, keywords, etc)
Slides

1C-3 (Time: 11:20 - 11:50)
TitleEfficient Sensitivity-Based Capacitance Modeling for Systematic and Random Geometric Variations
AuthorYu Bi (Delft Univ. of Tech., Netherlands), Pieter Harpe (Holst Centre/IMEC, Netherlands), *Nick van der Meijs (Delft Univ. of Tech., Netherlands)
Pagepp. 61 - 66
Detailed information (abstract, keywords, etc)
Slides

1C-4 (Time: 11:50 - 12:20)
TitleParallel Statistical Capacitance Extraction of On-Chip Interconnects with an Improved Geometric Variation Model
Author*Wenjian Yu, Chao Hu (Tsinghua Univ., China), Wangyang Zhang (Carnegie Mellon Univ., U.S.A.)
Pagepp. 67 - 72
Detailed information (abstract, keywords, etc)
Slides


Session 1D  University LSI Design Contest
Time: 10:20 - 12:20 Wednesday, January 26, 2011
Location: Room 416+417
Organizers: Masanori Hariyama (Tohoku Univ., Japan), Hiroshi Kawaguchi (Kobe Univ., Japan)

1D-1 (Time: 10:20 - 10:24)
TitleA H.264/MPEG-2 Dual Mode Video Decoder Chip Supporting Temporal/Spatial Scalable Video
Author*Cheng-An Chien, Yao-Chang Yang, Hsiu-Cheng Chang, Jia-Wei Chen, Cheng-Yen Chang, Jiun-In Guo, Jinn-Shyan Wang (National Chung Cheng Univ., Taiwan), Ching-Hwa Cheng (Feng Chia Univ., Taiwan)
Pagepp. 73 - 74
Detailed information (abstract, keywords, etc)
Slides

1D-2 (Time: 10:24 - 10:28)
TitleA Gate-level Pipelined 2.97GHz Self Synchronous FPGA in 65nm CMOS
Author*Benjamin Devlin, Makoto Ikeda, Kunihiro Asada (Univ. of Tokyo, Japan)
Pagepp. 75 - 76
Detailed information (abstract, keywords, etc)
Slides

1D-3 (Time: 10:28 - 10:32)
TitleA 4.32 mm2 170mW LDPC Decoder in 0.13µm CMOS for WiMax/Wi-Fi Applications
Author*Dan Bao, Chuan Wu, Yan Ying, Yun Chen, Xiao Yang Zeng (Fudan Univ., China)
Pagepp. 77 - 78
Detailed information (abstract, keywords, etc)

1D-4 (Time: 10:32 - 10:36)
TitleAll-Digital PMOS and NMOS Process Variability Monitor Utilizing Buffer Ring with Pulse Counter
Author*Jaehyun Jeong, Tetsuya Iizuka, Toru Nakura, Makoto Ikeda, Kunihiro Asada (Univ. of Tokyo, Japan)
Pagepp. 79 - 80
Detailed information (abstract, keywords, etc)

1D-5 (Time: 10:36 - 10:40)
TitleJitter Amplifier for Oscillator-Based True Random Number Generator
Author*Takehiko Amaki, Masanori Hashimoto, Takao Onoye (Osaka Univ., Japan)
Pagepp. 81 - 82
Detailed information (abstract, keywords, etc)
Slides

1D-6 (Time: 10:40 - 10:44)
TitleA 65nm Flip-Flop Array to Measure Soft Error Resiliency against High-Energy Neutron and Alpha Particles
Author*Jun Furuta (Kyoto Univ., Japan), Chikara Hamanaka, Kazutoshi Kobayashi (Kyoto Inst. of Tech., Japan), Hidetoshi Onodera (Kyoto Univ., Japan)
Pagepp. 83 - 84
Detailed information (abstract, keywords, etc)
Slides

1D-7 (Time: 10:44 - 10:48)
TitleDual-Phase Pipeline Circuit Design Automation with a Built-in Performance Adjusting Mechanism
AuthorYu-Tzu Tsai, Cheng-Chih Tsai (Feng Chia Univ., Taiwan), *Cheng-An Chien (National Chung Cheng Univ., Taiwan), Ching-Hwa Cheng (Feng Chia Univ., Taiwan), Jiun-In Guo (National Chung Cheng Univ., Taiwan)
Pagepp. 85 - 86
Detailed information (abstract, keywords, etc)

1D-8 (Time: 10:48 - 10:52)
TitleGeyser-2: The Second Prototype CPU with Fine-grained Run-time Power Gating
Author*Lei Zhao, Daisuke Ikebuchi, Yoshiki Saito, Masahiro Kamata, Naomi Seki, Yu Kojima, Hideharu Amano (Keio Univ., Japan), Satoshi Koyama, Tatsunori Hashida, Yusuke Umahashi, Daiki Masuda, Kimiyoshi Usami (Shibaura Inst. of Tech., Japan), Kazuki Kimura, Mitaro Namiki (Tokyo Univ. of Agri. and Tech., Japan), Seidai Takeda, Hiroshi Nakamura (Univ. of Tokyo, Japan), Masaaki Kondo (Univ. of Electro-Communications, Japan)
Pagepp. 87 - 88
Detailed information (abstract, keywords, etc)
Slides

1D-9 (Time: 10:52 - 10:56)
TitleAn Implementation of an Asychronous FPGA Based on LEDR/Four-Phase-Dual-Rail Hybrid Architecture
Author*Yoshiya Komatsu, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ., Japan)
Pagepp. 89 - 90
Detailed information (abstract, keywords, etc)
Slides

1D-10 (Time: 10:56 - 11:00)
TitleDesign and Chip Implementation of a Heterogeneous Multi-core DSP
Author*Shuming Chen, Xiaowen Chen, Yi Xu, Jianghua Wan, Jianzhuang Lu, Xiangyuan Liu, Shenggang Chen (National Univ. of Defense Tech., China)
Pagepp. 91 - 92
Detailed information (abstract, keywords, etc)
Slides

1D-11 (Time: 11:00 - 11:04)
TitleA Low-Power Management Technique for High-Performance Domino Circuits
AuthorYu-Tzu Tsai, Cheng-Chih Tsai (Feng Chia Univ., Taiwan), *Cheng-An Chien (National Chung Cheng Univ., Taiwan), Ching-Hwa Cheng (Feng Chia Univ., Taiwan), Jiun-In Guo (National Chung Cheng Univ., Taiwan)
Pagepp. 93 - 94
Detailed information (abstract, keywords, etc)

1D-12 (Time: 11:04 - 11:08)
TitleDesign and Evaluation of Variable Stages Pipeline Processor Chip
Author*Tomoyuki Nakabayashi, Takahiro Sasaki, Kazuhiko Ohno, Toshio Kondo (Mie Univ., Japan)
Pagepp. 95 - 96
Detailed information (abstract, keywords, etc)
Slides

1D-13 (Time: 11:08 - 11:12)
TitleTurboVG: A HW/SW Co-Designed Multi-Core OpenVG Accelerator for Vector Graphics Applications with Embedded Power Profiler
Author*Shuo-Hung Chen, Hsiao-Mei Lin, Ching-Chou Hsieh, Chih-Tsun Huang, Jing-Jia Liou, Yeh-Ching Chung (National Tsing Hua Univ., Taiwan)
Pagepp. 97 - 98
Detailed information (abstract, keywords, etc)
Slides

1D-14 (Time: 11:12 - 11:16)
TitleDesign and Implementation of a High Performance Closed-Loop MIMO Communications with Ultra Low Complexity Handset
Author*Yu-Han Yuan, Wei-Ming Chen, Hsi-Pin Ma (National Tsing Hua Univ., Taiwan)
Pagepp. 99 - 100
Detailed information (abstract, keywords, etc)
Slides

1D-15 (Time: 11:16 - 11:20)
TitleA 58-63.6GHz Quadrature PLL Frequency Synthesizer Using Dual-Injection Technique
Author*Ahmed Musa, Rui Murakami, Takahiro Sato, Win Chiavipas, Kenichi Okada, Akira Matsuzawa (Tokyo Inst. of Tech., Japan)
Pagepp. 101 - 102
Detailed information (abstract, keywords, etc)
Slides

1D-16 (Time: 11:20 - 11:24)
TitleAn Ultra-low-voltage LC-VCO with a Frequency Extension Circuit for Future 0.5-V Clock Generation
Author*Wei Deng, Kenichi Okada, Akira Matsuzawa (Tokyo Inst. of Tech., Japan)
Pagepp. 103 - 104
Detailed information (abstract, keywords, etc)
Slides

1D-17 (Time: 11:24 - 11:28)
TitleA 32Gbps Low Propagation Delay 4x4 Switch IC for Feedback-Based System in 0.13µm CMOS Technology
AuthorYu-Hao Hsu, Yang-Syu Lin, Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu, Fan-Ta Chen, Min-Sheng Kao, *Wei-Chih Lai, YarSun Hsu (National Tsing Hua Univ., Taiwan)
Pagepp. 105 - 106
Detailed information (abstract, keywords, etc)
Slides

1D-18 (Time: 11:28 - 11:32)
TitleA Fully Integrated Shock Wave Transmitter with an On-Chip Dipole Antenna for Pulse Beam-Formability in 0.18-μm CMOS
Author*Nguyen Ngoc Mai Khanh, Masahiro Sasaki, Kunihiro Asada (Univ. of Tokyo, Japan)
Pagepp. 107 - 108
Detailed information (abstract, keywords, etc)
Slides

1D-19 (Time: 11:32 - 11:36)
TitleAn On-Chip Characterizing System for Within-Die Delay Variation Measurement of Individual Standard Cells in 65-nm CMOS
Author*Xin Zhang, Koichi Ishida, Makoto Takamiya, Takayasu Sakurai (Univ. of Tokyo, Japan)
Pagepp. 109 - 110
Detailed information (abstract, keywords, etc)
Slides

1D-21 (Time: 11:36 - 11:40)
TitleRobust and Efficient Baseband Receiver Design for MB-OFDM UWB System
AuthorWen Fan, *Chiu-Sing Choy (Chinese Univ. of Hong Kong, Hong Kong)
Pagepp. 111 - 112
Detailed information (abstract, keywords, etc)

1D-22 (Time: 11:40 - 11:44)
TitleA 95-nA, 523ppm/°C, 0.6-µW CMOS Current Reference Circuit with Subthreshold MOS Resistor Ladder
Author*Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa (Kobe Univ., Japan)
Pagepp. 113 - 114
Detailed information (abstract, keywords, etc)
Slides

1D-23 (Time: 11:44 - 11:48)
TitleA 80-400 MHz 74 dB-DR Gm-C Low-Pass Filter With a Unique Auto-Tuning System
Author*Ting Gao, Wei Li, Ning Li, Junyan Ren (Fudan Univ., China)
Pagepp. 115 - 116
Detailed information (abstract, keywords, etc)
Slides

1D-24 (Time: 11:48 - 11:52)
TitleAn Adaptively Biased Low-Dropout Regulator with Transient Enhancement
Author*Chenchang Zhan, Wing-Hung Ki (Hong Kong Univ. of Science and Tech., Hong Kong)
Pagepp. 117 - 118
Detailed information (abstract, keywords, etc)
Slides

1D-25 (Time: 11:52 - 11:56)
TitleA Low-Power Triple-Mode Sigma-Delta DAC for Reconfigurable (WCDMA/TD-SCDMA/GSM) Transmitters
Author*Dong Qiu, Ting Yi, Zhiliang Hong (Fudan Univ., China)
Pagepp. 119 - 120
Detailed information (abstract, keywords, etc)

1D-26 (Time: 11:56 - 12:00)
TitleA Simple Non-coherent Solution to the UWB-IR Communication
Author*Mohiuddin Hafiz, Nobuo Sasaki, Kentaro Kimoto, Takamaro Kikkawa (Hiroshima Univ., Japan)
Pagepp. 121 - 122
Detailed information (abstract, keywords, etc)
Slides


Session 2A  Scheduling Techniques for Embedded Systems
Time: 13:40 - 15:40 Wednesday, January 26, 2011
Location: Room 411+412
Chairs: Dip Goswami (Tech. Univ. of Munich, Germany), Naehyuck Chang (Seoul National Univ., Republic of Korea)

2A-1 (Time: 13:40 - 14:10)
TitleThermally Optimal Stop-Go Scheduling of Task Graphs with Real-Time Constraints
Author*Pratyush Kumar, Lothar Thiele (ETH Zürich, Switzerland)
Pagepp. 123 - 128
Detailed information (abstract, keywords, etc)
Slides

2A-2 (Time: 14:10 - 14:40)
TitleRegister Allocation for Write Activity Minimization on Non-volatile Main Memory
AuthorYazhi Huang, Tiantian Liu, *Jason Xue (City Univ. of Hong Kong, Hong Kong)
Pagepp. 129 - 134
Detailed information (abstract, keywords, etc)

2A-3 (Time: 14:40 - 15:10)
TitleLeakage Conscious DVS Scheduling for Peak Temperature Minimization
AuthorVivek Chaturvedi, *Gang Quan (Florida International Univ., U.S.A.)
Pagepp. 135 - 140
Detailed information (abstract, keywords, etc)
Slides

2A-4 (Time: 15:10 - 15:40)
TitleReconfiguration-aware Real-Time Scheduling under QoS Constraint
AuthorHessam Kooti, *Deepak Mishra, Eli Bozorgzadeh (Univ. of California, Irvine, U.S.A.)
Pagepp. 141 - 146
Detailed information (abstract, keywords, etc)


Session 2B  Memory Architecture and Buffer Optimization
Time: 13:40 - 15:40 Wednesday, January 26, 2011
Location: Room 413
Chairs: Yu Wang (Tsinghua Univ., China), Yinhe Han (Chinese Academy of Sciences, China)

2B-1 (Time: 13:40 - 14:10)
TitleTemplate-based Memory Access Engine for Accelerators in SoCs
Author*Bin Li, Zhen Fang, Ravi Iyer (Intel Corp., U.S.A.)
Pagepp. 147 - 153
Detailed information (abstract, keywords, etc)
Slides

2B-2 (Time: 14:10 - 14:40)
TitleRealization and Performance Comparison of Sequential and Weak Memory Consistency Models in Network-on-Chip based Multi-core Systems
Author*Abdul Naeem, Xiaowen Chen, Zhonghai Lu, Axel Jantsch (Royal Inst. of Tech., Sweden)
Pagepp. 154 - 159
Detailed information (abstract, keywords, etc)
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2B-3 (Time: 14:40 - 15:10)
TitleNetwork-on-Chip Router Design with Buffer-Stealing
AuthorWan-Ting Su, *Jih-Sheng Shen, Pao-Ann Hsiung (National Chung Cheng Univ., Taiwan)
Pagepp. 160 - 164
Detailed information (abstract, keywords, etc)
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2B-4 (Time: 15:10 - 15:40)
TitleMinimizing Buffer Requirements for Throughput Constrained Parallel Execution of Synchronous Dataflow Graph
AuthorTae-ho Shin (Seoul National Univ., Republic of Korea), Hyunok Oh (Hanyang Univ., Republic of Korea), *Soonhoi Ha (Seoul National Univ., Republic of Korea)
Pagepp. 165 - 170
Detailed information (abstract, keywords, etc)
Slides


Session 2C  Modeling for Signal and Power Integrity
Time: 13:40 - 15:40 Wednesday, January 26, 2011
Location: Room 414+415
Chairs: Hideki Asai (Shizuoka Univ., Japan), Kimihiro Ogawa (STARC, Japan)

2C-1 (Time: 13:40 - 14:10)
TitleA Fast Approximation Technique for Power Grid Analysis
Author*Mysore Sriram (Intel Corp., India)
Pagepp. 171 - 175
Detailed information (abstract, keywords, etc)
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2C-2 (Time: 14:10 - 14:40)
TitleEquivalent Lumped Element Models for Various n-Port Through Silicon Vias Networks
Author*Khaled Salah Mohamed (Mentor Graphics, Egypt), Hani Ragai (Ain-Shams Univ., Egypt), Yehea Ismail (Nile Univ., Egypt), Alaa El Rouby (Mentor Graphics, Egypt)
Pagepp. 176 - 183
Detailed information (abstract, keywords, etc)
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2C-3 (Time: 14:40 - 15:10)
TitleClock Tree Optimization for Electromagnetic Compatibility (EMC)
Author*Xuchu Hu, Matthew R. Guthaus (Univ. of California, Santa Cruz, U.S.A.)
Pagepp. 184 - 189
Detailed information (abstract, keywords, etc)
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2C-4 (Time: 15:10 - 15:40)
TitlePulser Gating: A Clock Gating of Pulsed-Latch Circuits
Author*Sangmin Kim, Inhak Han, Seungwhun Paik, Youngsoo Shin (KAIST, Republic of Korea)
Pagepp. 190 - 195
Detailed information (abstract, keywords, etc)
Slides


Session 2D  Special Session: Emerging Memory Technologies and Its Implication on Circuit Design and Architectures
Time: 13:40 - 15:40 Wednesday, January 26, 2011
Location: Room 416+417
Organizer: Yuan Xie (Pennsylvania State Univ., U.S.A.)

2D-1 (Time: 13:40 - 14:10)
Title(Invited Paper) Circuit Design Challenges in Embedded Memory and Resistive RAM (RRAM) for Mobile SoC and 3D-IC
AuthorMeng-Fan Chang (National Tsing Hua Univ., Taiwan), Pi-Feng Chiu, Shyh-Shyuan Sheu (ITRI, Taiwan)
Pagepp. 197 - 203
Detailed information (abstract, keywords, etc)

2D-2 (Time: 14:10 - 14:40)
Title(Invited Paper) Emerging Sensing Techniques for Emerging Memories
AuthorYiran Chen (Univ. of Pittsburgh, U.S.A.), Hai Li (Polytechnic Institute of New York Univ., U.S.A.)
Pagepp. 204 - 210
Detailed information (abstract, keywords, etc)

2D-3 (Time: 14:40 - 15:10)
Title(Invited Paper) A Frequent-Value Based PRAM Memory Architecture
AuthorGuangyu Sun, Dimin Liu, Jin Ouyang, Yuan Xie (Pennsylvania State Univ., U.S.A.)
Pagepp. 211 - 216
Detailed information (abstract, keywords, etc)

2D-4 (Time: 15:10 - 15:40)
Title(Invited Paper) Two-Terminal Resistive Switches (Memristors) for Memory and Logic Applications
AuthorWei Lu, Kuk-Hwan Kim, Ting Chang, Siddharth Gaba (Univ. of Michigan, U.S.A.)
Pagepp. 217 - 223
Detailed information (abstract, keywords, etc)


Session 3A  High-Level Embedded Systems Design Techniques
Time: 16:00 - 18:00 Wednesday, January 26, 2011
Location: Room 411+412
Chairs: Yuko Hara-Azumi (Ritsumeikan Univ., Japan), Yiran Chen (Univ. of Pittsburgh, U.S.A.)

3A-1 (Time: 16:00 - 16:30)
TitleCo-design of Cyber-Physical Systems via Controllers with Flexible Delay Constraints
Author*Dip Goswami, Reinhard Schneider, Samarjit Chakraborty (Tech. Univ. of Munich, Germany)
Pagepp. 225 - 230
Detailed information (abstract, keywords, etc)
Slides

3A-2 (Time: 16:30 - 17:00)
TitleEnhanced Heterogeneous Code Cache Management Scheme for Dynamic Binary Translation
Author*Ang-Chih Hsieh, Chun-Cheng Liu, TingTing Hwang (National Tsing Hua Univ., Taiwan)
Pagepp. 231 - 236
Detailed information (abstract, keywords, etc)

3A-3 (Time: 17:00 - 17:30)
TitleFast Hybrid Simulation for Accurate Decoded Video Quality Assessment on MPSoC Platforms with Resource Constraints
Author*Deepak Gangadharan (National Univ. of Singapore, Singapore), Samarjit Chakraborty (Tech. Univ. of Munich, Germany), Roger Zimmermann (National Univ. of Singapore, Singapore)
Pagepp. 237 - 242
Detailed information (abstract, keywords, etc)
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3A-4 (Time: 17:30 - 18:00)
TitleOn the Interplay of Loop Caching, Code Compression, and Cache Configuration
AuthorMarisha Rawlins, *Ann Gordon-Ross (Univ. of Florida, U.S.A.)
Pagepp. 243 - 248
Detailed information (abstract, keywords, etc)
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Session 3B  Timing, Power, and Thermal Issues
Time: 16:00 - 18:00 Wednesday, January 26, 2011
Location: Room 413
Chair: Deming Chen (Univ. of Illinois, Urbana-Champaign, U.S.A.)

3B-1 (Time: 16:00 - 16:30)
TitlePath Criticality Computation in Parameterized Statistical Timing Analysis
Author*Jaeyong Chung (Univ. of Texas, Austin, U.S.A.), Jinjun Xiong, Vladimir Zolotov (IBM, U.S.A.), Jacob A. Abraham (Univ. of Texas, Austin, U.S.A.)
Pagepp. 249 - 254
Detailed information (abstract, keywords, etc)
Slides

3B-2 (Time: 16:30 - 17:00)
TitleRun-Time Adaptable On-Chip Thermal Triggers
Author*Pratyush Kumar, David Atienza (EPFL, Switzerland)
Pagepp. 255 - 260
Detailed information (abstract, keywords, etc)
Slides

3B-3 (Time: 17:00 - 17:30)
TitleRethinking Thermal Via Planning with Timing-Power-Temperature Dependence for 3D ICs
AuthorKan Wang, *Yuchun Ma, Sheqin Dong, Yu Wang, Xianlong Hong (Tsinghua Univ., China), Jason Cong (Univ. of California, Los Angeles, U.S.A.)
Pagepp. 261 - 266
Detailed information (abstract, keywords, etc)
Slides

3B-4 (Time: 17:30 - 18:00)
TitleThe Impact of Inverse Narrow Width Effect on Sub-threshold Device Sizing
AuthorJun Zhou, *Senthil Jayapal, Jan Stuyt, Jos Huisken, Harmke de Groot (Holst Centre/IMEC, Netherlands)
Pagepp. 267 - 272
Detailed information (abstract, keywords, etc)
Slides


Session 3C  Special Session: Post-Silicon Techniques to Counter Process and Electrical Parameter Variability
Time: 16:00 - 18:00 Wednesday, January 26, 2011
Location: Room 414+415
Chair: Jing-Jia Liou (National Tsing Hua Univ., Taiwan)

3C-1 (Time: 16:00 - 16:30)
Title(Invited Paper) Post-silicon Bug Detection for Variation Induced Electrical Bugs
AuthorMing Gao, Peter Lisherness, Kwang-Ting (Tim) Cheng (Univ. of California, Santa Barbara, U.S.A.)
Pagepp. 273 - 278
Detailed information (abstract, keywords, etc)

3C-2 (Time: 16:30 - 17:00)
Title(Invited Paper) Diagnosis-assisted Supply Voltage Configuration to Increase Performance Yield of Cell-Based Designs
AuthorJing-Jia Liou, Ying-Yen Chen, Chun-Chia Chen, Chung-Yen Chien, Kuo-Li Wu (National Tsing Hua Univ., Taiwan)
Pagepp. 279 - 284
Detailed information (abstract, keywords, etc)

3C-3 (Time: 17:00 - 17:30)
Title(Invited Paper) Run-Time Adaptive Performance Compensation using On-chip Sensors
AuthorMasanori Hashimoto (Osaka Univ. & JST, CREST, Japan)
Pagepp. 285 - 290
Detailed information (abstract, keywords, etc)

3C-4 (Time: 17:30 - 18:00)
Title(Invited Paper) The Alarms Project: A Hardware/Software Approach to Addressing Parameter Variations
AuthorDavid Brooks (Harvard Univ., U.S.A.)
Pagep. 291
Detailed information (abstract, keywords, etc)


Session 3D  Special Session: Recent Advances in Verification and Debug
Time: 16:00 - 18:00 Wednesday, January 26, 2011
Location: Room 416+417
Chair: Chung-Yang (Ric) Huang (National Taiwan Univ., Taiwan)

3D-1 (Time: 16:00 - 16:24)
Title(Invited Paper) Automatic Formal Verification of Reconfigurable DSPs
AuthorMiroslav N. Velev, Ping Gao (Aries Design Automation, U.S.A.)
Pagepp. 293 - 296
Detailed information (abstract, keywords, etc)

3D-2 (Time: 16:24 - 16:48)
Title(Invited Paper) SoC HW/SW Verification and Validation
AuthorChung-Yang Huang, Yu-Fan Yin, Chih-Jen Hsu (National Taiwan Univ., Taiwan), Thomas B. Huang, Ting-Mao Chang (InPA Systems, Inc., U.S.A.)
Pagepp. 297 - 300
Detailed information (abstract, keywords, etc)

3D-3 (Time: 16:48 - 17:12)
Title(Invited Paper) Utilizing High Level Design Information to Speed up Post-silicon Debugging
AuthorMasahiro Fujita (Univ. of Tokyo and CREST, Japan)
Pagepp. 301 - 305
Detailed information (abstract, keywords, etc)

3D-4 (Time: 17:12 - 17:36)
Title(Invited Paper) From RTL to Silicon: The Case for Automated Debug
AuthorAndreas Veneris, Brian Keng (Univ. of Toronto, Canada), Sean Safarpour (Vennsa Technologies, Inc., Canada)
Pagepp. 306 - 310
Detailed information (abstract, keywords, etc)

3D-5 (Time: 17:36 - 18:00)
Title(Invited Paper) Multi-Core Parallel Simulation of System-Level Description Languages
AuthorRainer Dömer, Weiwei Chen, Xu Han (Univ. of California, Irvine, U.S.A.), Andreas Gerstlauer (Univ. of Texas, Austin, U.S.A.)
Pagepp. 311 - 316
Detailed information (abstract, keywords, etc)



Thursday, January 27, 2011

Session 2K  Keynote Session II
Time: 9:00 - 10:00 Thursday, January 27, 2011
Location: Room 503
Chair: Kunihiro Asada (Univ. of Tokyo, Japan)

2K-1 (Time: 9:00 - 10:00)
Title(Keynote Address) Managing Increasing Complexity through Higher-Level of Abstraction: What the Past Has Taught Us about the Future
AuthorAjoy Bose (Atrenta Inc., U.S.A.)
Detailed information (abstract, keywords, etc)


Session 4A  Design Automation for Emerging Technologies
Time: 10:20 - 12:20 Thursday, January 27, 2011
Location: Room 411+412
Chairs: Hai Li (Polytechnic Institute of New York Univ., U.S.A.), Yu Wang (Tsinghua Univ., China)

4A-1 (Time: 10:20 - 10:50)
TitleVariation-aware Logic Mapping for Crossbar Nano-architectures
AuthorMasoud Zamani (Northeastern Univ., U.S.A.), *Mehdi B. Tahoori (Karlsruhe Inst. of Tech., Germany)
Pagepp. 317 - 322
Detailed information (abstract, keywords, etc)

4A-2 (Time: 10:50 - 11:20)
TitleRouting with Graphene Nanoribbons
AuthorTan Yan, Qiang Ma, Scott Chilstedt, *Martin Wong, Deming Chen (Univ. of Illinois, Urbana-Champaign, U.S.A.)
Pagepp. 323 - 329
Detailed information (abstract, keywords, etc)

4A-3 (Time: 11:20 - 11:50)
TitleILP-Based Inter-Die Routing for 3D ICs
AuthorChia-Jen Chang, Pao-Jen Huang, *Tai-Chen Chen, Chien-Nan Jimmy Liu (National Central Univ., Taiwan)
Pagepp. 330 - 335
Detailed information (abstract, keywords, etc)

4A-4 (Time: 11:50 - 12:20)
TitleCELONCEL: Effective Design Technique for 3-D Monolithic Integration targeting High Performance Integrated Circuits
Author*Shashikanth Bobba (Swiss Inst. of Tech. Lausanne (EPFL), Switzerland), Ashutosh Chakraborty (Univ. of Texas, Austin, U.S.A.), Olivier Thomas, Perrine Batude, Thomas Ernst, Olivier Faynot (LETI, France), David Z. Pan (Univ. of Texas, Austin, U.S.A.), Giovanni De Micheli (Swiss Inst. of Tech. Lausanne (EPFL), Switzerland)
Pagepp. 336 - 343
Detailed information (abstract, keywords, etc)


Session 4B  Novel Network-on-Chip Architecture Design
Time: 10:20 - 12:20 Thursday, January 27, 2011
Location: Room 413
Chairs: Yoshinori Takeuchi (Osaka Univ., Japan), Hao Yu (Nanyang Technological Univ., Singapore)

4B-1 (Time: 10:20 - 10:50)
TitleOPAL: A Multi-Layer Hybrid Photonic NoC for 3D ICs
Author*Sudeep Pasricha, Shirish Bahirat (Colorado State Univ., U.S.A.)
Pagepp. 345 - 350
Detailed information (abstract, keywords, etc)

4B-2 (Time: 10:50 - 11:20)
TitleEnabling Quality-of-Service in Nanophotonic Network-on-Chip
Author*Jin Ouyang, Yuan Xie (Pennsylvania State Univ., U.S.A.)
Pagepp. 351 - 356
Detailed information (abstract, keywords, etc)
Slides

4B-3 (Time: 11:20 - 11:50)
TitleVertical Interconnects Squeezing in Symmetric 3D Mesh Network-on-Chip
Author*Cheng Liu, Lei Zhang, Yinhe Han, Xiaowei Li (Chinese Academy of Sciences, China)
Pagepp. 357 - 362
Detailed information (abstract, keywords, etc)
Slides

4B-4 (Time: 11:50 - 12:20)
TitlePower-efficient Tree-based Multicast Support for Networks-on-Chip
Author*Wenmin Hu (National Univ. of Defense Tech., China), Zhonghai Lu, Axel Jantsch (Royal Inst. of Tech., Sweden), Hengzhu Liu (National Univ. of Defense Tech., China)
Pagepp. 363 - 368
Detailed information (abstract, keywords, etc)
Slides


Session 4C  Architecture Design and Reliability
Time: 10:20 - 12:20 Thursday, January 27, 2011
Location: Room 414+415
Chairs: Shigeru Yamashita (Ritsumeikan Univ., Japan), Rolf Drechsler (Univ. of Bremen, Germany)

4C-1 (Time: 10:20 - 10:50)
TitleArea-Efficient FPGA Logic Elements: Architecture and Synthesis
Author*Jason Anderson (Univ. of Toronto, Canada), Qiang Wang (Xilinx, Inc., U.S.A.)
Pagepp. 369 - 375
Detailed information (abstract, keywords, etc)
Slides

4C-2 (Time: 10:50 - 11:20)
TitleSelectively Patterned Masks: Structured ASIC with Asymptotically ASIC Performance
Author*Donkyu Baek, Insup Shin, Seungwhun Paik, Youngsoo Shin (KAIST, Republic of Korea)
Pagepp. 376 - 381
Detailed information (abstract, keywords, etc)
Slides

4C-3 (Time: 11:20 - 11:50)
TitleA Robust ECO Engine by Resource-Constraint-Aware Technology Mapping and Incremental Routing Optimization
Author*Shao-Lun Huang, Chi-An Wu, Kai-Fu Tang, Chang-Hong Hsu, Chung-Yang (Ric) Huang (National Taiwan Univ., Taiwan)
Pagepp. 382 - 387
Detailed information (abstract, keywords, etc)
Slides

4C-4 (Time: 11:50 - 12:20)
TitleSETmap: A Soft Error Tolerant Mapping Algorithm for FPGA Designs with Low Power
AuthorChi-Chen Peng, Chen Dong, *Deming Chen (Univ. of Illinois, Urbana-Champaign, U.S.A.)
Pagepp. 388 - 393
Detailed information (abstract, keywords, etc)


Session 4D  Special Session: Advanced Patterning and DFM for Nanolithography beyond 22nm
Time: 10:20 - 12:20 Thursday, January 27, 2011
Location: Room 416+417
Organizer: David Z. Pan (Univ. of Texas, Austin, U.S.A.)

4D-1 (Time: 10:20 - 10:50)
Title(Invited Paper) All-out Fight against Yield Losses by Design-manufacturing Collaboration in Nano-lithography Era
AuthorSoichi Inoue, Sachiko Kobayashi (Toshiba, Japan)
Pagepp. 395 - 401
Detailed information (abstract, keywords, etc)

4D-2 (Time: 10:50 - 11:20)
Title(Invited Paper) EUV Lithography: Prospects and Challenges
AuthorSam Sivakumar (Intel Corp., U.S.A.)
Pagep. 402
Detailed information (abstract, keywords, etc)

4D-3 (Time: 11:20 - 11:50)
Title(Invited Paper) Future Electron-Beam Lithography and Implications on Design and CAD Tools
AuthorJack J.H. Chen, Faruk Krecinic, Jen-Hom Chen, Raymond P.S. Chen, Burn J. Lin (Taiwan Semiconductor Manufacturing Company, Taiwan)
Pagepp. 403 - 404
Detailed information (abstract, keywords, etc)

4D-4 (Time: 11:50 - 12:20)
Title(Invited Paper) Exploration of VLSI CAD Researches for Early Design Rule Evaluation
AuthorChul-Hong Park (Samsung Electronics, Republic of Korea), David Z. Pan (Univ. of Texas, Austin, U.S.A.), Kevin Lucas (Synopsys, U.S.A.)
Pagepp. 405 - 406
Detailed information (abstract, keywords, etc)


Session 5A  System-Level Simulation
Time: 13:40 - 15:40 Thursday, January 27, 2011
Location: Room 411+412
Chairs: Nagisa Ishiura (Kwansei Gakuin Univ., Japan), Bo-Cheng Charles Lai (National Chiao Tung Univ., Taiwan)

5A-1 (Time: 13:40 - 14:10)
TitleHandling Dynamic Frequency Changes in Statically Scheduled Cycle-Accurate Simulation
Author*Marius Gligor, Frédéric Pétrot (TIMA Laboratory, CNRS/INP Grenoble/UJF, France)
Pagepp. 407 - 412
Detailed information (abstract, keywords, etc)
Slides

5A-2 (Time: 14:10 - 14:40)
TitleCoarse-grained Simulation Method for Performance Evaluation a of Shared Memory System
Author*Ryo Kawahara, Kenta Nakamura, Kouichi Ono, Takeo Nakada (IBM Research, Japan), Yoshifumi Sakamoto (Global Business Services, IBM Japan, Japan)
Pagepp. 413 - 418
Detailed information (abstract, keywords, etc)
Slides

5A-3 (Time: 14:40 - 15:10)
TitleT-SPaCS EA Two-Level Single-Pass Cache Simulation Methodology
AuthorWei Zang, *Ann Gordon-Ross (Univ. of Florida, U.S.A.)
Pagepp. 419 - 424
Detailed information (abstract, keywords, etc)
Slides

5A-4 (Time: 15:10 - 15:40)
TitleFast Data-Cache Modeling for Native Co-Simulation
Author*Héctor Posadas, Luis Diaz, Eugenio Villar (Univ. of Cantabria, Spain)
Pagepp. 425 - 430
Detailed information (abstract, keywords, etc)
Slides


Session 5B  Resilient and Thermal-Aware NoC Design
Time: 13:40 - 15:40 Thursday, January 27, 2011
Location: Room 413
Chairs: Michihiro Koibuchi (NII, Japan), Pao-Ann Hsiung (National Chung Cheng Univ., Taiwan)

5B-1 (Time: 13:40 - 14:10)
TitleOn the Design and Analysis of Fault Tolerant NoC Architecture Using Spare Routers
Author*Yung-Chang Chang (ITRI, Taiwan), Ching-Te Chiu (National Tsing Hua Univ., Taiwan), Shih-Yin Lin, Chung-Kai Liu (ITRI, Taiwan)
Pagepp. 431 - 436
Detailed information (abstract, keywords, etc)

5B-2 (Time: 14:10 - 14:40)
TitleA Resilient On-chip Router Design Through Data Path Salvaging
Author*Cheng Liu, Lei Zhang, Yinhe Han, Xiaowei Li (Chinese Academy of Sciences, China)
Pagepp. 437 - 442
Detailed information (abstract, keywords, etc)
Slides

5B-3 (Time: 14:40 - 15:10)
TitleNS-FTR: A Fault Tolerant Routing Scheme for Networks on Chip with Permanent and Runtime Intermittent Faults
Author*Sudeep Pasricha, Yong Zou (Colorado State Univ., U.S.A.)
Pagepp. 443 - 448
Detailed information (abstract, keywords, etc)

5B-4 (Time: 15:10 - 15:40)
TitleA Thermal-aware Application Specific Routing Algorithm for Network-on-Chip Design
Author*Zhiliang Qian, Chi-Ying Tsui (Hong Kong Univ. of Science and Tech., Hong Kong)
Pagepp. 449 - 454
Detailed information (abstract, keywords, etc)
Slides


Session 5C  High-Level and Logic Synthesis
Time: 13:40 - 15:40 Thursday, January 27, 2011
Location: Room 414+415
Chairs: Kiyoung Choi (Seoul National Univ., Republic of Korea), Shigeru Yamashita (Ritsumeikan Univ., Japan)

5C-1 (Time: 13:40 - 14:10)
TitleAn Efficient Hybrid Engine to Perform Range Analysis and Allocate Integer Bit-widths for Arithmetic Circuits
Author*Yu Pang (Chongqing Univ. of Posts and Telecommunications, China), Katarzyna Radecka, Zeljko Zilic (McGill Univ., Canada)
Pagepp. 455 - 460
Detailed information (abstract, keywords, etc)
Slides

5C-2 (Time: 14:10 - 14:40)
TitleRegister Pressure Aware Scheduling for High Level Synthesis
Author*Rami Beidas, Wai Sum Mong, Jianwen Zhu (Univ. of Toronto, Canada)
Pagepp. 461 - 466
Detailed information (abstract, keywords, etc)

5C-3 (Time: 14:40 - 15:10)
TitleParallel Cross-Layer Optimization of High-Level Synthesis and Physical Design
Author*James Williamson (Univ. of Colorado, Boulder, U.S.A.), Yinghai Lu (Northwestern Univ., U.S.A.), Li Shang (Univ. of Colorado, Boulder, U.S.A.), Hai Zhou (Northwestern Univ., U.S.A.), Xuan Zeng (Fudan Univ., China)
Pagepp. 467 - 472
Detailed information (abstract, keywords, etc)
Slides

5C-4 (Time: 15:10 - 15:40)
TitleNetwork Flow-based Simultaneous Retiming and Slack Budgeting for Low Power Design
AuthorBei Yu, Sheqin Dong, *Yuchun Ma, Tao Lin, Yu Wang (Tsinghua Univ., China), Song Chen, Satoshi GOTO (Waseda Univ., Japan)
Pagepp. 473 - 478
Detailed information (abstract, keywords, etc)
Slides


Session 5D  Designers' Forum: C-P-B Co-design/Co-verification Technology for DDR3 1.6G in Consumer Products
Time: 13:40 - 15:40 Thursday, January 27, 2011
Location: Room 416+417
Organizer: Koji Kato (Sony, Japan)

5D-1 (Time: 13:40 - 15:10)
Title(Panel Discussion) C-P-B Co-design/Co-verification Technology for DDR3 1.6G in Consumer Products
AuthorOrganizer: Koji Kato (Sony, Japan), Moderator: Makoto Nagata (Kobe Univ., Japan), Panelists: Keisuke Matsunami (Sony, Japan), Yoshinori Fukuba (Toshiba, Japan), Ji Zheng (Apache Design Solutions, U.S.A.), Jen-Tai Hsu (Global Unichip Corp., U.S.A.), CT Chiu (ASE, Taiwan)
Detailed information (abstract, keywords, etc)
Slides


Session 6A  Design Validation Techniques
Time: 16:00 - 18:00 Thursday, January 27, 2011
Location: Room 411+412
Chairs: Miroslav Velev (Aries Design Automation, U.S.A.), Kiyoharu Hamaguchi (Osaka Univ., Japan)

6A-1 (Time: 16:00 - 16:30)
TitleManaging Complexity in Design Debugging with Sequential Abstraction and Refinement
Author*Brian Keng, Andreas Veneris (Univ. of Toronto, Canada)
Pagepp. 479 - 484
Detailed information (abstract, keywords, etc)
Slides

6A-2 (Time: 16:30 - 17:00)
TitleFacilitating Unreachable Code Diagnosis and Debugging
AuthorHong-Zu Chou (National Taiwan Univ., Taiwan), *Kai-Hui Chang (Avery Design Systems, Inc., U.S.A.), Sy-Yen Kuo (National Taiwan Univ., Taiwan)
Pagepp. 485 - 490
Detailed information (abstract, keywords, etc)
Slides

6A-3 (Time: 17:00 - 17:30)
TitleDeterministic Test for the Reproduction and Detection of Board-Level Functional Failures
AuthorHongxia Fang (Duke Univ., U.S.A.), Zhiyuan Wang, Xinli Gu (Cisco Systems Inc., U.S.A.), *Krishnendu Chakrabarty (Duke Univ., U.S.A.)
Pagepp. 491 - 496
Detailed information (abstract, keywords, etc)

6A-4 (Time: 17:30 - 18:00)
TitleEquivalence Checking of Scheduling with Speculative Code Transformations in High-Level Synthesis
Author*Chi-Hui Lee, Che-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou (National Chiao Tung Univ., Taiwan)
Pagepp. 497 - 502
Detailed information (abstract, keywords, etc)


Session 6B  Clock Network Design
Time: 16:00 - 18:00 Thursday, January 27, 2011
Location: Room 413
Chairs: Yuchun Ma (Tsinghua Univ., China), Youngsoo Shin (KAIST, Republic of Korea)

6B-1 (Time: 16:00 - 16:30)
TitleAn Optimal Algorithm for Allocation, Placement, and Delay Assignment of Adjustable Delay Buffers for Clock Skew Minimization in Multi-Voltage Mode Designs
Author*Kyoung-Hwan Lim, Taewhan Kim (Seoul National Univ., Republic of Korea)
Pagepp. 503 - 508
Detailed information (abstract, keywords, etc)
Slides

6B-2 (Time: 16:30 - 17:00)
TitleOn Applying Erroneous Clock Gating Conditions to Further Cut Down Power
Author*Tak-Kei Lam, Xiaoqing Yang, Wai-Chung Tang, Yu-Liang Wu (Chinese Univ. of Hong Kong, Hong Kong)
Pagepp. 509 - 514
Detailed information (abstract, keywords, etc)

6B-3 (Time: 17:00 - 17:30)
TitleLow Power Discrete Voltage Assignment Under Clock Skew Scheduling
AuthorLi Li (Northwestern Univ., U.S.A.), Jian Sun (Fudan Univ., China), Yinghai Lu, *Hai Zhou (Northwestern Univ., U.S.A.), Xuan Zeng (Fudan Univ., China)
Pagepp. 515 - 520
Detailed information (abstract, keywords, etc)
Slides

6B-4 (Time: 17:30 - 18:00)
TitleA Practical Method for Multi-domain Clock Skew Optimization
Author*Yanling Zhi (Fudan Univ., China), Hai Zhou (Northwestern Univ., U.S.A.), Xuan Zeng (Fudan Univ., China)
Pagepp. 521 - 526
Detailed information (abstract, keywords, etc)
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Session 6C  Advances in Routing
Time: 16:00 - 18:00 Thursday, January 27, 2011
Location: Room 414+415
Chair: David Z. Pan (Univ. of Texas, Austin, U.S.A.)

6C-1 (Time: 16:00 - 16:30)
TitleEfficient Multi-Layer Obstacle-Avoiding Preferred Direction Rectilinear Steiner Tree Construction
Author*Jia-Ru Chuang, Jai-Ming Lin (National Cheng Kung Univ., Taiwan)
Pagepp. 527 - 532
Detailed information (abstract, keywords, etc)

6C-2 (Time: 16:30 - 17:00)
TitleCut-Demand Based Routing Resource Allocation and Consolidation for Routability Enhancement
Author*Fong-Yuan Chang (National Tsing Hua Univ., Taiwan), Sheng-Hsiung Chen (SpringSoft, Taiwan), Ren-Song Tsay, Wai-Kei Mak (National Tsing Hua Univ., Taiwan)
Pagepp. 533 - 538
Detailed information (abstract, keywords, etc)
Slides

6C-3 (Time: 17:00 - 17:30)
TitleNegotiation-Based Layer Assignment for Via Count and Via Overflow Minimization
Author*Wen-Hao Liu, Yih-Lang Li (National Chiao Tung Univ., Taiwan)
Pagepp. 539 - 544
Detailed information (abstract, keywords, etc)

6C-4 (Time: 17:30 - 18:00)
TitleWire Synthesizable Global Routing for Timing Closure
AuthorMichael Moffitt (IBM Corp., U.S.A.), *C. N. Sze (IBM Research, U.S.A.)
Pagepp. 545 - 550
Detailed information (abstract, keywords, etc)


Session 6D  Designers' Forum: Emerging Technologies for Wellness Applications
Time: 16:00 - 18:00 Thursday, January 27, 2011
Location: Room 416+417
Organizer: Hideki Yoshizawa (Fujitsu Labs., Japan)

6D-1 (Time: 16:00 - 16:30)
Title(Invited Paper) Biological Information Sensing Technologies for Medical, Health Care, and Wellness Applications
AuthorMasaharu Imai, Yoshinori Takeuchi, Keishi Sakanushi, Hirofumi Iwato (Osaka Univ., Japan)
Pagepp. 551 - 555
Detailed information (abstract, keywords, etc)
Slides

6D-2 (Time: 16:30 - 17:00)
Title(Invited Paper) Ultra-Low Power Microcontrollers for Portable, Wearable, and Implantable Medical Electronics
AuthorSrinivasa R. Sridhara (Texas Instruments, Inc., U.S.A.)
Pagepp. 556 - 560
Detailed information (abstract, keywords, etc)
Slides

6D-3 (Time: 17:00 - 17:30)
Title(Invited Paper) Human++: Wireless Autonomous Sensor Technology for Body Area Networks
AuthorValer Pop, Ruben de Francisco, Hans Pflug, Juan Santana, Huib Visser, Ruud Vullers, Harmke de Groot, Bert Gyselinckx (IMEC, Netherlands)
Pagepp. 561 - 566
Detailed information (abstract, keywords, etc)
Slides

6D-4 (Time: 17:30 - 18:00)
Title(Invited Paper) Healthcare of an Organization: Using Wearable Sensors and Feedback System for Energizing Workers
AuthorKoji Ara, Tomoaki Akitomi, Nobuo Sato, Satomi Tsuji, Miki Hayakawa, Yoshihiro Wakisaka, Norio Ohkubo, Rieko Otsuka, Fumiko Beniyama, Norihiko Moriwaki, Kazuo Yano (Hitachi, Ltd., Japan)
Pagepp. 567 - 572
Detailed information (abstract, keywords, etc)
Slides



Friday, January 28, 2011

Session 3K  Keynote Session III
Time: 9:00 - 10:00 Friday, January 28, 2011
Location: Room 503
Chair: Kunihiro Asada (Univ. of Tokyo, Japan)

3K-1 (Time: 9:00 - 10:00)
Title(Keynote Address) Robust Systems: From Clouds to Nanotubes
AuthorSubhasish Mitra (Stanford Univ., U.S.A.)
Detailed information (abstract, keywords, etc)


Session 7A  System Level Analysis and Optimization
Time: 10:20 - 12:20 Friday, January 28, 2011
Location: Room 411+412
Chairs: Hiroshi Saito (Aizu Univ., Japan), Lovic Ganchier (Kyushu Univ., Japan)

7A-1 (Time: 10:20 - 10:50)
TitleA Polynomial-Time Custom Instruction Identification Algorithm Based on Dynamic Programming
Author*Junwhan Ahn, Imyong Lee, Kiyoung Choi (Seoul National Univ., Republic of Korea)
Pagepp. 573 - 578
Detailed information (abstract, keywords, etc)
Slides

7A-2 (Time: 10:50 - 11:20)
TitleExploring the Fidelity-Efficiency Design Space using Imprecise Arithmetic
Author*Jiawei Huang, John Lach (Univ. of Virginia, U.S.A.)
Pagepp. 579 - 584
Detailed information (abstract, keywords, etc)
Slides

7A-3 (Time: 11:20 - 11:50)
TitleThroughput Optimization for Latency-Insensitive System with Minimal Queue Insertion
AuthorJuinn-Dar Huang, *Yi-Hang Chen, Ya-Chien Ho (National Chiao Tung Univ., Taiwan)
Pagepp. 585 - 590
Detailed information (abstract, keywords, etc)
Slides

7A-4 (Time: 11:50 - 12:20)
TitleA Fast and Effective Dynamic Trace-based Method for Analyzing Architectural Performance
Author*Yi-Siou Chen, Lih-Yih Chiou, Hsun-Hsiang Chang (National Cheng Kung Univ., Taiwan)
Pagepp. 591 - 596
Detailed information (abstract, keywords, etc)
Slides


Session 7B  NBTI and Power Gating
Time: 10:20 - 12:20 Friday, January 28, 2011
Location: Room 413
Chairs: Kimiyoshi Usami (Shibaura Inst. of Tech., Japan), Toshio Sudo (Shibaura Inst. of Tech., Japan)

7B-1 (Time: 10:20 - 10:50)
TitleControlling NBTI Degradation during Static Burn-in Testing
Author*Ashutosh Chakraborty, David Z. Pan (Univ. of Texas, Austin, U.S.A.)
Pagepp. 597 - 602
Detailed information (abstract, keywords, etc)

7B-2 (Time: 10:50 - 11:20)
TitleA Fine-Grained Technique of NBTI-Aware Voltage Scaling and Body Biasing for Standard Cell Based Designs
Author*Yongho Lee (Samsung Electronics, Republic of Korea), Taewhan Kim (Seoul National Univ., Republic of Korea)
Pagepp. 603 - 608
Detailed information (abstract, keywords, etc)

7B-3 (Time: 11:20 - 11:50)
TitleNBTI-Aware Power Gating Design
AuthorMing-Chao Lee, *Yu-Guang Chen, Ding-Kai Huang, Shih-Chieh Chang (National Tsing Hua Univ., Taiwan)
Pagepp. 609 - 614
Detailed information (abstract, keywords, etc)
Slides

7B-4 (Time: 11:50 - 12:20)
TitleRobust Power Gating Reactivation By Dynamic Wakeup Sequence Throttling
AuthorTung-Yeh Wu, Shih-Hsin Hu, *Jacob A. Abraham (Univ. of Texas, Austin, U.S.A.)
Pagepp. 615 - 620
Detailed information (abstract, keywords, etc)


Session 7C  Physical Design for Yield
Time: 10:20 - 12:20 Friday, January 28, 2011
Location: Room 414+415
Chair: Cliff Sze (IBM, U.S.A.)

7C-1 (Time: 10:20 - 10:50)
TitleRobust Clock Tree Synthesis with Timing Yield Optimization for 3D-ICs
Author*Jae-Seok Yang, Jiwoo Pak (Univ. of Texas, Austin, U.S.A.), Xin Zhao, Sung Kyu Lim (Georgia Tech, U.S.A.), David Z. Pan (Univ. of Texas, Austin, U.S.A.)
Pagepp. 621 - 626
Detailed information (abstract, keywords, etc)

7C-2 (Time: 10:50 - 11:20)
TitleTrack Routing Optimizing Timing and Yield
AuthorXin Gao, *Luca Macchiarulo (Univ. of Hawaii, Manoa, U.S.A.)
Pagepp. 627 - 632
Detailed information (abstract, keywords, etc)

7C-3 (Time: 11:20 - 11:50)
TitleSimultaneous Redundant Via Insertion and Line End Extension for Yield Optimization
AuthorShing-Tung Lin (National Tsing Hua Univ., Taiwan), Kuang-Yao Lee (Taiwan Semiconductor Manufacturing Company, Taiwan), *Ting-Chi Wang (National Tsing Hua Univ., Taiwan), Cheng-Kok Koh (Purdue Univ., U.S.A.), Kai-Yuan Chao (Intel Corp., U.S.A.)
Pagepp. 633 - 638
Detailed information (abstract, keywords, etc)
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7C-4 (Time: 11:50 - 12:20)
TitlePruning-based Trace Signal Selection Algorithm
Author*Kang Zhao, Jinian Bian (Tsinghua Univ., China)
Pagepp. 639 - 644
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Session 7D  Special Session: Virtualization, Programming, and Energy-Efficiency Design Issues of Embedded Systems
Time: 10:20 - 12:20 Friday, January 28, 2011
Location: Room 416+417
Organizer: Tei-Wei Kuo (National Taiwan Univ., Taiwan)

7D-1 (Time: 10:20 - 10:50)
Title(Invited Paper) Temporal and Spatial Isolation in a Virtualization Layer for Multi-core Processor based Information Appliances
AuthorTatsuo Nakajima, Yuki Kinebuchi, Hiromasa Shimada, Alexandre Courbot, Tsung-Han Lin (Waseda Univ., Japan)
Pagepp. 645 - 652
Detailed information (abstract, keywords, etc)

7D-2 (Time: 10:50 - 11:20)
Title(Invited Paper) Mathematical Limits of Parallel Computation for Embedded Systems
AuthorJason Loew, Jesse Elwell, Dmitry Ponomarev, Patrick H. Madden (SUNY Binghamton Computer Science Department, U.S.A.)
Pagepp. 653 - 660
Detailed information (abstract, keywords, etc)

7D-3 (Time: 11:20 - 11:50)
Title(Invited Paper) An Enhanced Leakage-Aware Scheduler for Dynamically Reconfigurable FPGAs
AuthorJen-Wei Hsieh (National Taiwan Univ. of Science and Tech., Taiwan), Yuan-Hao Chang (National Taipei Univ. of Tech., Taiwan), Wei-Li Lee (National Taiwan Univ. of Science and Tech., Taiwan)
Pagepp. 661 - 667
Detailed information (abstract, keywords, etc)

7D-4 (Time: 11:50 - 12:20)
Title(Invited Paper) Power Management Strategies in Data Transmission
AuthorTiefei Zhang (Zhejiang Univ., China), Ying-Jheng Chen, Che-Wei Chang, Chuan-Yue Yang, Tei-Wei Kuo (National Taiwan Univ., Taiwan), Tianzhou Chen (Zhejiang Univ., China)
Pagepp. 668 - 675
Detailed information (abstract, keywords, etc)


Session 8A  Modeling and Design for Variability
Time: 13:40 - 15:40 Friday, January 28, 2011
Location: Room 411+412
Chairs: Fedor G. Pikus (Mentor Graphics, U.S.A.), Hidetoshi Matsuoka (Fujitsu Laboratories, Japan)

8A-1 (Time: 13:40 - 14:10)
TitleRobust Spatial Correlation Extraction with Limited Sample via L1-Norm Penalty
AuthorMingzhi Gao, *Zuochang Ye, Dajie Zeng, Yan Wang, Zhiping Yu (Tsinghua Univ., China)
Pagepp. 677 - 682
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8A-2 (Time: 14:10 - 14:40)
TitleDevice-Parameter Estimation with On-chip Variation Sensors Considering Random Variability
Author*Ken-ichi Shinkai, Masanori Hashimoto (Osaka Univ., Japan)
Pagepp. 683 - 688
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8A-3 (Time: 14:40 - 15:10)
TitleAccounting for Inherent Circuit Resilience and Process Variations in Analyzing Gate Oxide Reliability
AuthorJianxin Fang, *Sachin S. Sapatnekar (Univ. of Minnesota, U.S.A.)
Pagepp. 689 - 694
Detailed information (abstract, keywords, etc)

8A-4 (Time: 15:10 - 15:40)
TitleVariation-Tolerant and Self-Repair Design Methodology for Low Temperature Polycrystalline Silicon Liquid Crystal and Organic Light Emitting Diode Displays
Author*Chih-Hsiang Ho, Chao Lu, Debabrata Mohapatra, Kaushik Roy (Purdue Univ., U.S.A.)
Pagepp. 695 - 700
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Session 8B  Test for Reliability and Yield
Time: 13:40 - 15:40 Friday, January 28, 2011
Location: Room 413
Chairs: Yu Huang (Mentor Graphics, U.S.A.), Yoshinobu Higami (Ehime Univ., Japan)

8B-1 (Time: 13:40 - 14:10)
TitleA Physical-Location-Aware Fault Redistribution for Maximum IR-Drop Reduction
Author*Fu-Wei Chen, Shih-Liang Chen, Yung-Sheng Lin, TingTing Hwang (National Tsing Hua Univ., Taiwan)
Pagepp. 701 - 706
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8B-2 (Time: 14:10 - 14:40)
TitleOn the Impact of Gate Oxide Degradation on SRAM Dynamic and Static Write-ability
Author*Vikas Chandra, Robert Aitken (ARM, U.S.A.)
Pagepp. 707 - 712
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8B-3 (Time: 14:40 - 15:10)
TitleA Self-Testing and Calibration Method for Embedded Successive Approximation Register ADC
AuthorXuan-Lun Huang, Ping-Ying Kang (National Taiwan Univ., Taiwan), Hsiu-Ming Chang (Univ. of California, Santa Barbara, U.S.A.), *Jiun-Lang Huang (National Taiwan Univ., Taiwan), Yung-Fa Chou, Yung-Pin Lee, Ding-Ming Kwai, Cheng-Wen Wu (ITRI, Taiwan)
Pagepp. 713 - 718
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8B-4 (Time: 15:10 - 15:40)
TitleOn-chip Dynamic Signal Sequence Slicing for Efficient Post-Silicon Debugging
Author*Yeonbok Lee, Takeshi Matsumoto, Masahiro Fujita (Univ. of Tokyo, Japan)
Pagepp. 719 - 724
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Session 8C  System-Level Power Optimization
Time: 13:40 - 15:40 Friday, January 28, 2011
Location: Room 414+415
Chairs: Masanori Muroyama (Tohoku Univ., Japan), Lih-Yih Chiou (National Cheng Kung Univ., Taiwan)

8C-1 (Time: 13:40 - 14:10)
TitleAVS-Aware Power-Gate Sizing for Maximum Performance and Power Efficiency of Power-Constrained Processors
AuthorAbhishek Sinkar, *Nam Sung Kim (Univ. of Wisconsin-Madison, U.S.A.)
Pagepp. 725 - 730
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8C-2 (Time: 14:10 - 14:40)
TitleEnergy/Reliability Trade-offs in Fault-Tolerant Event-Triggered Distributed Embedded Systems
Author*Junhe Gan (Tech. Univ. of Denmark, Denmark), Flavius Gruian (Lund Univ., Sweden), Paul Pop, Jan Madsen (Tech. Univ. of Denmark, Denmark)
Pagepp. 731 - 736
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8C-3 (Time: 14:40 - 15:10)
TitleProfile Assisted Online System-Level Performance and Power Estimation for Dynamic Reconfigurable Embedded Systems
AuthorJingqing Mu, *Roman Lysecky (Univ. of Arizona, U.S.A.)
Pagepp. 737 - 742
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8C-4 (Time: 15:10 - 15:40)
TitleBattery-Aware Task Scheduling in Distributed Mobile Systems with Lifetime Constraint
AuthorJiayin Li, *Meikang Qiu (Univ. of Kentucky, U.S.A.), Jian-wei Niu (Beihang Univ., China), Tianzhou Chen (Zhejiang Univ., China)
Pagepp. 743 - 748
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Session 8D  Designers' Forum: State-of-The-Art SoCs and Design Methodologies
Time: 13:40 - 15:40 Friday, January 28, 2011
Location: Room 416+417
Organizer: Masaitsu Nakajima (Panasonic, Japan)

8D-1 (Time: 13:40 - 14:04)
Title(Invited Paper) Advanced System LSIs for Home 3D System
AuthorTakao Suzuki (Panasonic Corp., Japan)
Pagepp. 749 - 754
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8D-2 (Time: 14:04 - 14:28)
Title(Invited Paper) Development of Low Power and High Performance Application Processor (T6G) for Multimedia Mobile Applications
AuthorYoshiyuki Kitasho, Yu Kikuchi, Takayoshi Shimazawa, Yasuo Ohara, Masafumi Takahashi, Yoshio Masubuchi, Yukihito Oowaki (Toshiba Corp. Semiconductor Company, Japan)
Pagepp. 755 - 759
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8D-3 (Time: 14:28 - 14:52)
Title(Invited Paper) Design Constraint of Fine Grain Supply Voltage Control LSI
AuthorAtsuki Inoue (Fujitsu Labs., Japan)
Pagepp. 760 - 765
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8D-4 (Time: 14:52 - 15:16)
Title(Invited Paper) FPGA Prototyping using Behavioral Synthesis for Improving Video Processing Algorithm and FHD TV SoC Design
AuthorMasaru Takahashi (Renesas Electronics Corp., Japan)
Pagepp. 766 - 769
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8D-5 (Time: 15:16 - 15:40)
Title(Invited Paper) An RTL-to-GDS2 Design Methodology for Advanced System LSI
AuthorNobuyuki Nishiguchi (STARC, Japan)
Pagepp. 770 - 774
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Session 9A  Printability and Mask Optimization
Time: 16:00 - 18:00 Friday, January 28, 2011
Location: Room 411+412
Chairs: Murakata Masami (STARC, Japan), Zheng Shi (Zhejiang Univ., China)

9A-1 (Time: 16:00 - 16:30)
TitleHigh Performance Lithographic Hotspot Detection using Hierarchically Refined Machine Learning
AuthorDuo Ding (Univ. of Texas, Austin, U.S.A.), Andres Torres, Fedor Pikus (Mentor Graphics Corp., U.S.A.), *David Pan (Univ. of Texas, Austin, U.S.A.)
Pagepp. 775 - 780
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9A-2 (Time: 16:30 - 17:00)
TitleRapid Layout Pattern Classification
Author*Jen-Yi Wuu (Univ. of California, Santa Barbara, U.S.A.), Fedor G. Pikus, Andres Torres (Mentor Graphics Corp., U.S.A.), Malgorzata Marek-Sadowska (Univ. of California, Santa Barbara, U.S.A.)
Pagepp. 781 - 786
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9A-3 (Time: 17:00 - 17:30)
TitleMask Cost Reduction with Circuit Performance Consideration for Self-Aligned Double Patterning
AuthorHongbo Zhang, Yuelin Du, *Martin D. F. Wong (Univ. of Illinois, Urbana-Champaign, U.S.A.), Kai-Yuan Chao (Intel Corp., U.S.A.)
Pagepp. 787 - 792
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9A-4 (Time: 17:30 - 18:00)
TitlePost-Routing Layer Assignment for Double Patterning
Author*Jian Sun (Fudan Univ., China), Yinghai Lu, Hai Zhou (Northwestern Univ., U.S.A.), Xuan Zeng (Fudan Univ., China)
Pagepp. 793 - 798
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Session 9B  Emerging Solutions in Scan Testing
Time: 16:00 - 18:00 Friday, January 28, 2011
Location: Room 413
Chairs: Seiji Kajihara (Kyusyu Inst. of Tech., Japan), Ting Ting Hwang (National Tsing Hua Univ., Taiwan)

9B-1 (Time: 16:00 - 16:30)
TitleFault Simulation and Test Generation for Clock Delay Faults
Author*Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi (Ehime Univ., Japan), Kewal K. Saluja (Univ. of Wisconsin-Madison, U.S.A.)
Pagepp. 799 - 805
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9B-2 (Time: 16:30 - 17:00)
TitleCompression-Aware Capture Power Reduction for At-Speed Testing
Author*Jia Li (Tsinghua Univ., China), Qiang Xu (Chinese Univ. of Hong Kong, Hong Kong), Dong Xiang (Tsinghua Univ., China)
Pagepp. 806 - 811
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9B-3 (Time: 17:00 - 17:30)
TitleFault Diagnosis Aware ATE Assisted Test Response Compaction
AuthorJoseph Howard, *Sudhakar M Reddy (Univ. of Iowa, U.S.A.), Irith Pomeranz (Purdue Univ., U.S.A.), Bernd Becker (Univ. of Freiburg, Germany)
Pagepp. 812 - 817
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9B-4 (Time: 17:30 - 18:00)
TitleSecure Scan Design Using Shift Register Equivalents against Differential Behavior Attack
Author*Hideo Fujiwara (NAIST, Japan), Katsuya Fujiwara, Hideo Tamamoto (Akita Univ., Japan)
Pagepp. 818 - 823
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Session 9C  Clock and Package
Time: 16:00 - 18:00 Friday, January 28, 2011
Location: Room 414+415
Chair: Yasuhiro Takashima (Univ. of Kitakyushu, Japan)

9C-1 (Time: 16:00 - 16:30)
TitleAn Efficient Algorithm of Adjustable Delay Buffer Insertion for Clock Skew Minimization in Multiple Dynamic Supply Voltage Designs
AuthorKuan-Yu Lin, *Hong-Ting Lin, Tsung-Yi Ho (National Cheng Kung Univ., Taiwan)
Pagepp. 825 - 830
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9C-2 (Time: 16:30 - 17:00)
TitleAn Integer Programming Placement Approach to FPGA Clock Power Reduction
Author*Alireza Rakhshanfar, Jason Anderson (Univ. of Toronto, Canada)
Pagepp. 831 - 836
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9C-3 (Time: 17:00 - 17:30)
TitleRow-Based Area-Array I/O Design Planning in Concurrent Chip-Package Design Flow
AuthorRen-Jie Lee, *Hung-Ming Chen (National Chiao Tung Univ., Taiwan)
Pagepp. 837 - 842
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9C-4 (Time: 17:30 - 18:00)
TitleA Provably Good Approximation Algorithm for Rectangle Escape Problem with Application to PCB Routing
AuthorQiang Ma, Hui Kong, *Martin D. F. Wong (Univ. of Illinois, Urbana-Champaign, U.S.A.), Evangeline F. Y. Young (Chinese Univ. of Hong Kong, Hong Kong)
Pagepp. 843 - 848
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Session 9D  Designers' Forum: Advanced Packaging and 3D Technologies
Time: 16:00 - 18:00 Friday, January 28, 2011
Location: Room 416+417
Organizer: Yoshio Masubuchi (Toshiba, Japan)

9D-1 (Time: 16:00 - 17:30)
Title(Panel Discussion) Advanced Packaging and 3D Technologies
AuthorOrganizer: Yoshio Masubuchi (Toshiba, Japan), Moderator: Kenichi Osada (Hitachi, Japan), Panelists: Geert Van der Plas (IMEC, Belgium), Hirokazu Ezawa (Toshiba, Japan), Yasumitsu Orii (IBM, Japan), Yoichi Hiruta (J-Devices, Japan), Chris Cheung (Cadence Design Systems, U.S.A.)
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