Wednesday, January 26, 2011 |
Room 411+412 | Room 413 | Room 414+415 | Room 416+417 |
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Opening and Keynote Session I 8:30 - 10:00 |
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10:20 - 12:20 |
10:20 - 12:20 |
10:20 - 12:20 |
10:20 - 12:20 |
13:40 - 15:40 |
13:40 - 15:40 |
13:40 - 15:40 |
13:40 - 15:40 |
16:00 - 18:00 |
16:00 - 18:00 |
16:00 - 18:00 |
16:00 - 18:00 |
Thursday, January 27, 2011 |
Room 411+412 | Room 413 | Room 414+415 | Room 416+417 |
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Keynote Session II 9:00 - 10:00 |
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10:20 - 12:20 |
10:20 - 12:20 |
10:20 - 12:20 |
10:20 - 12:20 |
13:40 - 15:40 |
13:40 - 15:40 |
13:40 - 15:40 |
13:40 - 15:40 |
16:00 - 18:00 |
16:00 - 18:00 |
16:00 - 18:00 |
16:00 - 18:00 |
Friday, January 28, 2011 |
Room 411+412 | Room 413 | Room 414+415 | Room 416+417 |
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Keynote Session III 9:00 - 10:00 |
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10:20 - 12:20 |
10:20 - 12:20 |
10:20 - 12:20 |
10:20 - 12:20 |
13:40 - 15:40 |
13:40 - 15:40 |
13:40 - 15:40 |
13:40 - 15:40 |
16:00 - 18:00 |
16:00 - 18:00 |
16:00 - 18:00 |
16:00 - 18:00 |
Wednesday, January 26, 2011 |
Title | (Keynote Address) Non-Volatile Memory and Normally-Off Computing |
Author | Takayuki Kawahara (Hitachi, Japan) |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Analog Circuit Verification by Statistical Model Checking |
Author | *Ying-Chih Wang, Anvesh Komuravelli, Paolo Zuliani, Edmund M. Clarke (Carnegie Mellon Univ., U.S.A.) |
Page | pp. 1 - 6 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | FSM Model Abstraction for Analog/Mixed-Signal Circuits by Learning from I/O Trajectories |
Author | *Chenjie Gu, Jaijeet Roychowdhury (Univ. of California, Berkeley, U.S.A.) |
Page | pp. 7 - 12 |
Detailed information (abstract, keywords, etc) |
Title | A Structured Parallel Periodic Arnoldi Shooting Algorithm for RF-PSS Analysis based on GPU Platforms |
Author | Xue-Xin Liu (Univ. of California, Riverside, U.S.A.), Hao Yu (Nanyang Technological Univ., Singapore), Jacob Relles, *Sheldon X.-D. Tan (Univ. of California, Riverside, U.S.A.) |
Page | pp. 13 - 18 |
Detailed information (abstract, keywords, etc) |
Title | Hierarchical Exact Symbolic Analysis of Large Analog Integrated Circuits By Symbolic Stamps |
Author | *Hui Xu, Guoyong Shi, Xiaopeng Li (Shanghai Jiao Tong Univ., China) |
Page | pp. 19 - 24 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Geometry Variations Analysis of TiO2 Thin-Film and Spintronic Memristors |
Author | *Miao Hu, Hai Li (Polytechnic Institute of New York Univ., U.S.A.), Yiran Chen (Univ. of Pittsburgh, U.S.A.), Xiaobin Wang (Seagate Technology, U.S.A.), Robinson Pino (AFRL/RITC, U.S.A.) |
Page | pp. 25 - 30 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | AdaMS: Adaptive MLC/SLC Phase-Change Memory Design for File Storage |
Author | *Xiangyu Dong, Yuan Xie (Pennsylvania State Univ., U.S.A.) |
Page | pp. 31 - 36 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | System Accuracy Estimation of SRAM-based Device Authentication |
Author | Joonsoo Kim, Joonsoo Lee, *Jacob A. Abraham (Univ. of Texas, Austin, U.S.A.) |
Page | pp. 37 - 42 |
Detailed information (abstract, keywords, etc) |
Title | On-Chip Hybrid Power Supply System for Wireless Sensor Nodes |
Author | *Wulong Liu, Yu Wang, Wei Liu, Yuchun Ma (Tsinghua Univ., China), Yuan Xie (Pennsylvania State Univ., U.S.A.), Huazhong Yang (Tsinghua Univ., China) |
Page | pp. 43 - 48 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | A Moment-Matching Scheme for the Passivity-Preserving Model Order Reduction of Indefinite Descriptor Systems with Possible Polynomial Parts |
Author | *Zheng Zhang (Massachusetts Inst. of Tech., U.S.A.), Qing Wang, Ngai Wong (Univ. of Hong Kong, Hong Kong), Luca Daniel (Massachusetts Inst. of Tech., U.S.A.) |
Page | pp. 49 - 54 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Balanced Truncation for Time-Delay Systems Via Approximate Gramians |
Author | *Xiang Wang, Qing Wang, Zheng Zhang, Quan Chen, Ngai Wong (Univ. of Hong Kong, Hong Kong) |
Page | pp. 55 - 60 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Efficient Sensitivity-Based Capacitance Modeling for Systematic and Random Geometric Variations |
Author | Yu Bi (Delft Univ. of Tech., Netherlands), Pieter Harpe (Holst Centre/IMEC, Netherlands), *Nick van der Meijs (Delft Univ. of Tech., Netherlands) |
Page | pp. 61 - 66 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Parallel Statistical Capacitance Extraction of On-Chip Interconnects with an Improved Geometric Variation Model |
Author | *Wenjian Yu, Chao Hu (Tsinghua Univ., China), Wangyang Zhang (Carnegie Mellon Univ., U.S.A.) |
Page | pp. 67 - 72 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | A H.264/MPEG-2 Dual Mode Video Decoder Chip Supporting Temporal/Spatial Scalable Video |
Author | *Cheng-An Chien, Yao-Chang Yang, Hsiu-Cheng Chang, Jia-Wei Chen, Cheng-Yen Chang, Jiun-In Guo, Jinn-Shyan Wang (National Chung Cheng Univ., Taiwan), Ching-Hwa Cheng (Feng Chia Univ., Taiwan) |
Page | pp. 73 - 74 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | A Gate-level Pipelined 2.97GHz Self Synchronous FPGA in 65nm CMOS |
Author | *Benjamin Devlin, Makoto Ikeda, Kunihiro Asada (Univ. of Tokyo, Japan) |
Page | pp. 75 - 76 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | A 4.32 mm2 170mW LDPC Decoder in 0.13µm CMOS for WiMax/Wi-Fi Applications |
Author | *Dan Bao, Chuan Wu, Yan Ying, Yun Chen, Xiao Yang Zeng (Fudan Univ., China) |
Page | pp. 77 - 78 |
Detailed information (abstract, keywords, etc) |
Title | All-Digital PMOS and NMOS Process Variability Monitor Utilizing Buffer Ring with Pulse Counter |
Author | *Jaehyun Jeong, Tetsuya Iizuka, Toru Nakura, Makoto Ikeda, Kunihiro Asada (Univ. of Tokyo, Japan) |
Page | pp. 79 - 80 |
Detailed information (abstract, keywords, etc) |
Title | Jitter Amplifier for Oscillator-Based True Random Number Generator |
Author | *Takehiko Amaki, Masanori Hashimoto, Takao Onoye (Osaka Univ., Japan) |
Page | pp. 81 - 82 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | A 65nm Flip-Flop Array to Measure Soft Error Resiliency against High-Energy Neutron and Alpha Particles |
Author | *Jun Furuta (Kyoto Univ., Japan), Chikara Hamanaka, Kazutoshi Kobayashi (Kyoto Inst. of Tech., Japan), Hidetoshi Onodera (Kyoto Univ., Japan) |
Page | pp. 83 - 84 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Dual-Phase Pipeline Circuit Design Automation with a Built-in Performance Adjusting Mechanism |
Author | Yu-Tzu Tsai, Cheng-Chih Tsai (Feng Chia Univ., Taiwan), *Cheng-An Chien (National Chung Cheng Univ., Taiwan), Ching-Hwa Cheng (Feng Chia Univ., Taiwan), Jiun-In Guo (National Chung Cheng Univ., Taiwan) |
Page | pp. 85 - 86 |
Detailed information (abstract, keywords, etc) |
Title | Geyser-2: The Second Prototype CPU with Fine-grained Run-time Power Gating |
Author | *Lei Zhao, Daisuke Ikebuchi, Yoshiki Saito, Masahiro Kamata, Naomi Seki, Yu Kojima, Hideharu Amano (Keio Univ., Japan), Satoshi Koyama, Tatsunori Hashida, Yusuke Umahashi, Daiki Masuda, Kimiyoshi Usami (Shibaura Inst. of Tech., Japan), Kazuki Kimura, Mitaro Namiki (Tokyo Univ. of Agri. and Tech., Japan), Seidai Takeda, Hiroshi Nakamura (Univ. of Tokyo, Japan), Masaaki Kondo (Univ. of Electro-Communications, Japan) |
Page | pp. 87 - 88 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | An Implementation of an Asychronous FPGA Based on LEDR/Four-Phase-Dual-Rail Hybrid Architecture |
Author | *Yoshiya Komatsu, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ., Japan) |
Page | pp. 89 - 90 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Design and Chip Implementation of a Heterogeneous Multi-core DSP |
Author | *Shuming Chen, Xiaowen Chen, Yi Xu, Jianghua Wan, Jianzhuang Lu, Xiangyuan Liu, Shenggang Chen (National Univ. of Defense Tech., China) |
Page | pp. 91 - 92 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | A Low-Power Management Technique for High-Performance Domino Circuits |
Author | Yu-Tzu Tsai, Cheng-Chih Tsai (Feng Chia Univ., Taiwan), *Cheng-An Chien (National Chung Cheng Univ., Taiwan), Ching-Hwa Cheng (Feng Chia Univ., Taiwan), Jiun-In Guo (National Chung Cheng Univ., Taiwan) |
Page | pp. 93 - 94 |
Detailed information (abstract, keywords, etc) |
Title | Design and Evaluation of Variable Stages Pipeline Processor Chip |
Author | *Tomoyuki Nakabayashi, Takahiro Sasaki, Kazuhiko Ohno, Toshio Kondo (Mie Univ., Japan) |
Page | pp. 95 - 96 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | TurboVG: A HW/SW Co-Designed Multi-Core OpenVG Accelerator for Vector Graphics Applications with Embedded Power Profiler |
Author | *Shuo-Hung Chen, Hsiao-Mei Lin, Ching-Chou Hsieh, Chih-Tsun Huang, Jing-Jia Liou, Yeh-Ching Chung (National Tsing Hua Univ., Taiwan) |
Page | pp. 97 - 98 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Design and Implementation of a High Performance Closed-Loop MIMO Communications with Ultra Low Complexity Handset |
Author | *Yu-Han Yuan, Wei-Ming Chen, Hsi-Pin Ma (National Tsing Hua Univ., Taiwan) |
Page | pp. 99 - 100 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | A 58-63.6GHz Quadrature PLL Frequency Synthesizer Using Dual-Injection Technique |
Author | *Ahmed Musa, Rui Murakami, Takahiro Sato, Win Chiavipas, Kenichi Okada, Akira Matsuzawa (Tokyo Inst. of Tech., Japan) |
Page | pp. 101 - 102 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | An Ultra-low-voltage LC-VCO with a Frequency Extension Circuit for Future 0.5-V Clock Generation |
Author | *Wei Deng, Kenichi Okada, Akira Matsuzawa (Tokyo Inst. of Tech., Japan) |
Page | pp. 103 - 104 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | A 32Gbps Low Propagation Delay 4x4 Switch IC for Feedback-Based System in 0.13µm CMOS Technology |
Author | Yu-Hao Hsu, Yang-Syu Lin, Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu, Fan-Ta Chen, Min-Sheng Kao, *Wei-Chih Lai, YarSun Hsu (National Tsing Hua Univ., Taiwan) |
Page | pp. 105 - 106 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | A Fully Integrated Shock Wave Transmitter with an On-Chip Dipole Antenna for Pulse Beam-Formability in 0.18-μm CMOS |
Author | *Nguyen Ngoc Mai Khanh, Masahiro Sasaki, Kunihiro Asada (Univ. of Tokyo, Japan) |
Page | pp. 107 - 108 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | An On-Chip Characterizing System for Within-Die Delay Variation Measurement of Individual Standard Cells in 65-nm CMOS |
Author | *Xin Zhang, Koichi Ishida, Makoto Takamiya, Takayasu Sakurai (Univ. of Tokyo, Japan) |
Page | pp. 109 - 110 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Robust and Efficient Baseband Receiver Design for MB-OFDM UWB System |
Author | Wen Fan, *Chiu-Sing Choy (Chinese Univ. of Hong Kong, Hong Kong) |
Page | pp. 111 - 112 |
Detailed information (abstract, keywords, etc) |
Title | A 95-nA, 523ppm/°C, 0.6-µW CMOS Current Reference Circuit with Subthreshold MOS Resistor Ladder |
Author | *Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa (Kobe Univ., Japan) |
Page | pp. 113 - 114 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | A 80-400 MHz 74 dB-DR Gm-C Low-Pass Filter With a Unique Auto-Tuning System |
Author | *Ting Gao, Wei Li, Ning Li, Junyan Ren (Fudan Univ., China) |
Page | pp. 115 - 116 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | An Adaptively Biased Low-Dropout Regulator with Transient Enhancement |
Author | *Chenchang Zhan, Wing-Hung Ki (Hong Kong Univ. of Science and Tech., Hong Kong) |
Page | pp. 117 - 118 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | A Low-Power Triple-Mode Sigma-Delta DAC for Reconfigurable (WCDMA/TD-SCDMA/GSM) Transmitters |
Author | *Dong Qiu, Ting Yi, Zhiliang Hong (Fudan Univ., China) |
Page | pp. 119 - 120 |
Detailed information (abstract, keywords, etc) |
Title | A Simple Non-coherent Solution to the UWB-IR Communication |
Author | *Mohiuddin Hafiz, Nobuo Sasaki, Kentaro Kimoto, Takamaro Kikkawa (Hiroshima Univ., Japan) |
Page | pp. 121 - 122 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Thermally Optimal Stop-Go Scheduling of Task Graphs with Real-Time Constraints |
Author | *Pratyush Kumar, Lothar Thiele (ETH Zürich, Switzerland) |
Page | pp. 123 - 128 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Register Allocation for Write Activity Minimization on Non-volatile Main Memory |
Author | Yazhi Huang, Tiantian Liu, *Jason Xue (City Univ. of Hong Kong, Hong Kong) |
Page | pp. 129 - 134 |
Detailed information (abstract, keywords, etc) |
Title | Leakage Conscious DVS Scheduling for Peak Temperature Minimization |
Author | Vivek Chaturvedi, *Gang Quan (Florida International Univ., U.S.A.) |
Page | pp. 135 - 140 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Reconfiguration-aware Real-Time Scheduling under QoS Constraint |
Author | Hessam Kooti, *Deepak Mishra, Eli Bozorgzadeh (Univ. of California, Irvine, U.S.A.) |
Page | pp. 141 - 146 |
Detailed information (abstract, keywords, etc) |
Title | Template-based Memory Access Engine for Accelerators in SoCs |
Author | *Bin Li, Zhen Fang, Ravi Iyer (Intel Corp., U.S.A.) |
Page | pp. 147 - 153 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Realization and Performance Comparison of Sequential and Weak Memory Consistency Models in Network-on-Chip based Multi-core Systems |
Author | *Abdul Naeem, Xiaowen Chen, Zhonghai Lu, Axel Jantsch (Royal Inst. of Tech., Sweden) |
Page | pp. 154 - 159 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Network-on-Chip Router Design with Buffer-Stealing |
Author | Wan-Ting Su, *Jih-Sheng Shen, Pao-Ann Hsiung (National Chung Cheng Univ., Taiwan) |
Page | pp. 160 - 164 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Minimizing Buffer Requirements for Throughput Constrained Parallel Execution of Synchronous Dataflow Graph |
Author | Tae-ho Shin (Seoul National Univ., Republic of Korea), Hyunok Oh (Hanyang Univ., Republic of Korea), *Soonhoi Ha (Seoul National Univ., Republic of Korea) |
Page | pp. 165 - 170 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | A Fast Approximation Technique for Power Grid Analysis |
Author | *Mysore Sriram (Intel Corp., India) |
Page | pp. 171 - 175 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Equivalent Lumped Element Models for Various n-Port Through Silicon Vias Networks |
Author | *Khaled Salah Mohamed (Mentor Graphics, Egypt), Hani Ragai (Ain-Shams Univ., Egypt), Yehea Ismail (Nile Univ., Egypt), Alaa El Rouby (Mentor Graphics, Egypt) |
Page | pp. 176 - 183 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Clock Tree Optimization for Electromagnetic Compatibility (EMC) |
Author | *Xuchu Hu, Matthew R. Guthaus (Univ. of California, Santa Cruz, U.S.A.) |
Page | pp. 184 - 189 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Pulser Gating: A Clock Gating of Pulsed-Latch Circuits |
Author | *Sangmin Kim, Inhak Han, Seungwhun Paik, Youngsoo Shin (KAIST, Republic of Korea) |
Page | pp. 190 - 195 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | (Invited Paper) Circuit Design Challenges in Embedded Memory and Resistive RAM (RRAM) for Mobile SoC and 3D-IC |
Author | Meng-Fan Chang (National Tsing Hua Univ., Taiwan), Pi-Feng Chiu, Shyh-Shyuan Sheu (ITRI, Taiwan) |
Page | pp. 197 - 203 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) Emerging Sensing Techniques for Emerging Memories |
Author | Yiran Chen (Univ. of Pittsburgh, U.S.A.), Hai Li (Polytechnic Institute of New York Univ., U.S.A.) |
Page | pp. 204 - 210 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) A Frequent-Value Based PRAM Memory Architecture |
Author | Guangyu Sun, Dimin Liu, Jin Ouyang, Yuan Xie (Pennsylvania State Univ., U.S.A.) |
Page | pp. 211 - 216 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) Two-Terminal Resistive Switches (Memristors) for Memory and Logic Applications |
Author | Wei Lu, Kuk-Hwan Kim, Ting Chang, Siddharth Gaba (Univ. of Michigan, U.S.A.) |
Page | pp. 217 - 223 |
Detailed information (abstract, keywords, etc) |
Title | Co-design of Cyber-Physical Systems via Controllers with Flexible Delay Constraints |
Author | *Dip Goswami, Reinhard Schneider, Samarjit Chakraborty (Tech. Univ. of Munich, Germany) |
Page | pp. 225 - 230 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Enhanced Heterogeneous Code Cache Management Scheme for Dynamic Binary Translation |
Author | *Ang-Chih Hsieh, Chun-Cheng Liu, TingTing Hwang (National Tsing Hua Univ., Taiwan) |
Page | pp. 231 - 236 |
Detailed information (abstract, keywords, etc) |
Title | Fast Hybrid Simulation for Accurate Decoded Video Quality Assessment on MPSoC Platforms with Resource Constraints |
Author | *Deepak Gangadharan (National Univ. of Singapore, Singapore), Samarjit Chakraborty (Tech. Univ. of Munich, Germany), Roger Zimmermann (National Univ. of Singapore, Singapore) |
Page | pp. 237 - 242 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | On the Interplay of Loop Caching, Code Compression, and Cache Configuration |
Author | Marisha Rawlins, *Ann Gordon-Ross (Univ. of Florida, U.S.A.) |
Page | pp. 243 - 248 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Path Criticality Computation in Parameterized Statistical Timing Analysis |
Author | *Jaeyong Chung (Univ. of Texas, Austin, U.S.A.), Jinjun Xiong, Vladimir Zolotov (IBM, U.S.A.), Jacob A. Abraham (Univ. of Texas, Austin, U.S.A.) |
Page | pp. 249 - 254 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Run-Time Adaptable On-Chip Thermal Triggers |
Author | *Pratyush Kumar, David Atienza (EPFL, Switzerland) |
Page | pp. 255 - 260 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Rethinking Thermal Via Planning with Timing-Power-Temperature Dependence for 3D ICs |
Author | Kan Wang, *Yuchun Ma, Sheqin Dong, Yu Wang, Xianlong Hong (Tsinghua Univ., China), Jason Cong (Univ. of California, Los Angeles, U.S.A.) |
Page | pp. 261 - 266 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | The Impact of Inverse Narrow Width Effect on Sub-threshold Device Sizing |
Author | Jun Zhou, *Senthil Jayapal, Jan Stuyt, Jos Huisken, Harmke de Groot (Holst Centre/IMEC, Netherlands) |
Page | pp. 267 - 272 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | (Invited Paper) Post-silicon Bug Detection for Variation Induced Electrical Bugs |
Author | Ming Gao, Peter Lisherness, Kwang-Ting (Tim) Cheng (Univ. of California, Santa Barbara, U.S.A.) |
Page | pp. 273 - 278 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) Diagnosis-assisted Supply Voltage Configuration to Increase Performance Yield of Cell-Based Designs |
Author | Jing-Jia Liou, Ying-Yen Chen, Chun-Chia Chen, Chung-Yen Chien, Kuo-Li Wu (National Tsing Hua Univ., Taiwan) |
Page | pp. 279 - 284 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) Run-Time Adaptive Performance Compensation using On-chip Sensors |
Author | Masanori Hashimoto (Osaka Univ. & JST, CREST, Japan) |
Page | pp. 285 - 290 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) The Alarms Project: A Hardware/Software Approach to Addressing Parameter Variations |
Author | David Brooks (Harvard Univ., U.S.A.) |
Page | p. 291 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) Automatic Formal Verification of Reconfigurable DSPs |
Author | Miroslav N. Velev, Ping Gao (Aries Design Automation, U.S.A.) |
Page | pp. 293 - 296 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) SoC HW/SW Verification and Validation |
Author | Chung-Yang Huang, Yu-Fan Yin, Chih-Jen Hsu (National Taiwan Univ., Taiwan), Thomas B. Huang, Ting-Mao Chang (InPA Systems, Inc., U.S.A.) |
Page | pp. 297 - 300 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) Utilizing High Level Design Information to Speed up Post-silicon Debugging |
Author | Masahiro Fujita (Univ. of Tokyo and CREST, Japan) |
Page | pp. 301 - 305 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) From RTL to Silicon: The Case for Automated Debug |
Author | Andreas Veneris, Brian Keng (Univ. of Toronto, Canada), Sean Safarpour (Vennsa Technologies, Inc., Canada) |
Page | pp. 306 - 310 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) Multi-Core Parallel Simulation of System-Level Description Languages |
Author | Rainer Dömer, Weiwei Chen, Xu Han (Univ. of California, Irvine, U.S.A.), Andreas Gerstlauer (Univ. of Texas, Austin, U.S.A.) |
Page | pp. 311 - 316 |
Detailed information (abstract, keywords, etc) |
Thursday, January 27, 2011 |
Title | (Keynote Address) Managing Increasing Complexity through Higher-Level of Abstraction: What the Past Has Taught Us about the Future |
Author | Ajoy Bose (Atrenta Inc., U.S.A.) |
Detailed information (abstract, keywords, etc) |
Title | Variation-aware Logic Mapping for Crossbar Nano-architectures |
Author | Masoud Zamani (Northeastern Univ., U.S.A.), *Mehdi B. Tahoori (Karlsruhe Inst. of Tech., Germany) |
Page | pp. 317 - 322 |
Detailed information (abstract, keywords, etc) |
Title | Routing with Graphene Nanoribbons |
Author | Tan Yan, Qiang Ma, Scott Chilstedt, *Martin Wong, Deming Chen (Univ. of Illinois, Urbana-Champaign, U.S.A.) |
Page | pp. 323 - 329 |
Detailed information (abstract, keywords, etc) |
Title | ILP-Based Inter-Die Routing for 3D ICs |
Author | Chia-Jen Chang, Pao-Jen Huang, *Tai-Chen Chen, Chien-Nan Jimmy Liu (National Central Univ., Taiwan) |
Page | pp. 330 - 335 |
Detailed information (abstract, keywords, etc) |
Title | CELONCEL: Effective Design Technique for 3-D Monolithic Integration targeting High Performance Integrated Circuits |
Author | *Shashikanth Bobba (Swiss Inst. of Tech. Lausanne (EPFL), Switzerland), Ashutosh Chakraborty (Univ. of Texas, Austin, U.S.A.), Olivier Thomas, Perrine Batude, Thomas Ernst, Olivier Faynot (LETI, France), David Z. Pan (Univ. of Texas, Austin, U.S.A.), Giovanni De Micheli (Swiss Inst. of Tech. Lausanne (EPFL), Switzerland) |
Page | pp. 336 - 343 |
Detailed information (abstract, keywords, etc) |
Title | OPAL: A Multi-Layer Hybrid Photonic NoC for 3D ICs |
Author | *Sudeep Pasricha, Shirish Bahirat (Colorado State Univ., U.S.A.) |
Page | pp. 345 - 350 |
Detailed information (abstract, keywords, etc) |
Title | Enabling Quality-of-Service in Nanophotonic Network-on-Chip |
Author | *Jin Ouyang, Yuan Xie (Pennsylvania State Univ., U.S.A.) |
Page | pp. 351 - 356 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Vertical Interconnects Squeezing in Symmetric 3D Mesh Network-on-Chip |
Author | *Cheng Liu, Lei Zhang, Yinhe Han, Xiaowei Li (Chinese Academy of Sciences, China) |
Page | pp. 357 - 362 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Power-efficient Tree-based Multicast Support for Networks-on-Chip |
Author | *Wenmin Hu (National Univ. of Defense Tech., China), Zhonghai Lu, Axel Jantsch (Royal Inst. of Tech., Sweden), Hengzhu Liu (National Univ. of Defense Tech., China) |
Page | pp. 363 - 368 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Area-Efficient FPGA Logic Elements: Architecture and Synthesis |
Author | *Jason Anderson (Univ. of Toronto, Canada), Qiang Wang (Xilinx, Inc., U.S.A.) |
Page | pp. 369 - 375 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Selectively Patterned Masks: Structured ASIC with Asymptotically ASIC Performance |
Author | *Donkyu Baek, Insup Shin, Seungwhun Paik, Youngsoo Shin (KAIST, Republic of Korea) |
Page | pp. 376 - 381 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | A Robust ECO Engine by Resource-Constraint-Aware Technology Mapping and Incremental Routing Optimization |
Author | *Shao-Lun Huang, Chi-An Wu, Kai-Fu Tang, Chang-Hong Hsu, Chung-Yang (Ric) Huang (National Taiwan Univ., Taiwan) |
Page | pp. 382 - 387 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | SETmap: A Soft Error Tolerant Mapping Algorithm for FPGA Designs with Low Power |
Author | Chi-Chen Peng, Chen Dong, *Deming Chen (Univ. of Illinois, Urbana-Champaign, U.S.A.) |
Page | pp. 388 - 393 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) All-out Fight against Yield Losses by Design-manufacturing Collaboration in Nano-lithography Era |
Author | Soichi Inoue, Sachiko Kobayashi (Toshiba, Japan) |
Page | pp. 395 - 401 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) EUV Lithography: Prospects and Challenges |
Author | Sam Sivakumar (Intel Corp., U.S.A.) |
Page | p. 402 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) Future Electron-Beam Lithography and Implications on Design and CAD Tools |
Author | Jack J.H. Chen, Faruk Krecinic, Jen-Hom Chen, Raymond P.S. Chen, Burn J. Lin (Taiwan Semiconductor Manufacturing Company, Taiwan) |
Page | pp. 403 - 404 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) Exploration of VLSI CAD Researches for Early Design Rule Evaluation |
Author | Chul-Hong Park (Samsung Electronics, Republic of Korea), David Z. Pan (Univ. of Texas, Austin, U.S.A.), Kevin Lucas (Synopsys, U.S.A.) |
Page | pp. 405 - 406 |
Detailed information (abstract, keywords, etc) |
Title | Handling Dynamic Frequency Changes in Statically Scheduled Cycle-Accurate Simulation |
Author | *Marius Gligor, Frédéric Pétrot (TIMA Laboratory, CNRS/INP Grenoble/UJF, France) |
Page | pp. 407 - 412 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Coarse-grained Simulation Method for Performance Evaluation a of Shared Memory System |
Author | *Ryo Kawahara, Kenta Nakamura, Kouichi Ono, Takeo Nakada (IBM Research, Japan), Yoshifumi Sakamoto (Global Business Services, IBM Japan, Japan) |
Page | pp. 413 - 418 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | T-SPaCS EA Two-Level Single-Pass Cache Simulation Methodology |
Author | Wei Zang, *Ann Gordon-Ross (Univ. of Florida, U.S.A.) |
Page | pp. 419 - 424 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Fast Data-Cache Modeling for Native Co-Simulation |
Author | *Héctor Posadas, Luis Diaz, Eugenio Villar (Univ. of Cantabria, Spain) |
Page | pp. 425 - 430 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | On the Design and Analysis of Fault Tolerant NoC Architecture Using Spare Routers |
Author | *Yung-Chang Chang (ITRI, Taiwan), Ching-Te Chiu (National Tsing Hua Univ., Taiwan), Shih-Yin Lin, Chung-Kai Liu (ITRI, Taiwan) |
Page | pp. 431 - 436 |
Detailed information (abstract, keywords, etc) |
Title | A Resilient On-chip Router Design Through Data Path Salvaging |
Author | *Cheng Liu, Lei Zhang, Yinhe Han, Xiaowei Li (Chinese Academy of Sciences, China) |
Page | pp. 437 - 442 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | NS-FTR: A Fault Tolerant Routing Scheme for Networks on Chip with Permanent and Runtime Intermittent Faults |
Author | *Sudeep Pasricha, Yong Zou (Colorado State Univ., U.S.A.) |
Page | pp. 443 - 448 |
Detailed information (abstract, keywords, etc) |
Title | A Thermal-aware Application Specific Routing Algorithm for Network-on-Chip Design |
Author | *Zhiliang Qian, Chi-Ying Tsui (Hong Kong Univ. of Science and Tech., Hong Kong) |
Page | pp. 449 - 454 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | An Efficient Hybrid Engine to Perform Range Analysis and Allocate Integer Bit-widths for Arithmetic Circuits |
Author | *Yu Pang (Chongqing Univ. of Posts and Telecommunications, China), Katarzyna Radecka, Zeljko Zilic (McGill Univ., Canada) |
Page | pp. 455 - 460 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Register Pressure Aware Scheduling for High Level Synthesis |
Author | *Rami Beidas, Wai Sum Mong, Jianwen Zhu (Univ. of Toronto, Canada) |
Page | pp. 461 - 466 |
Detailed information (abstract, keywords, etc) |
Title | Parallel Cross-Layer Optimization of High-Level Synthesis and Physical Design |
Author | *James Williamson (Univ. of Colorado, Boulder, U.S.A.), Yinghai Lu (Northwestern Univ., U.S.A.), Li Shang (Univ. of Colorado, Boulder, U.S.A.), Hai Zhou (Northwestern Univ., U.S.A.), Xuan Zeng (Fudan Univ., China) |
Page | pp. 467 - 472 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Network Flow-based Simultaneous Retiming and Slack Budgeting for Low Power Design |
Author | Bei Yu, Sheqin Dong, *Yuchun Ma, Tao Lin, Yu Wang (Tsinghua Univ., China), Song Chen, Satoshi GOTO (Waseda Univ., Japan) |
Page | pp. 473 - 478 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | (Panel Discussion) C-P-B Co-design/Co-verification Technology for DDR3 1.6G in Consumer Products |
Author | Organizer: Koji Kato (Sony, Japan), Moderator: Makoto Nagata (Kobe Univ., Japan), Panelists: Keisuke Matsunami (Sony, Japan), Yoshinori Fukuba (Toshiba, Japan), Ji Zheng (Apache Design Solutions, U.S.A.), Jen-Tai Hsu (Global Unichip Corp., U.S.A.), CT Chiu (ASE, Taiwan) |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Managing Complexity in Design Debugging with Sequential Abstraction and Refinement |
Author | *Brian Keng, Andreas Veneris (Univ. of Toronto, Canada) |
Page | pp. 479 - 484 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Facilitating Unreachable Code Diagnosis and Debugging |
Author | Hong-Zu Chou (National Taiwan Univ., Taiwan), *Kai-Hui Chang (Avery Design Systems, Inc., U.S.A.), Sy-Yen Kuo (National Taiwan Univ., Taiwan) |
Page | pp. 485 - 490 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Deterministic Test for the Reproduction and Detection of Board-Level Functional Failures |
Author | Hongxia Fang (Duke Univ., U.S.A.), Zhiyuan Wang, Xinli Gu (Cisco Systems Inc., U.S.A.), *Krishnendu Chakrabarty (Duke Univ., U.S.A.) |
Page | pp. 491 - 496 |
Detailed information (abstract, keywords, etc) |
Title | Equivalence Checking of Scheduling with Speculative Code Transformations in High-Level Synthesis |
Author | *Chi-Hui Lee, Che-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou (National Chiao Tung Univ., Taiwan) |
Page | pp. 497 - 502 |
Detailed information (abstract, keywords, etc) |
Title | An Optimal Algorithm for Allocation, Placement, and Delay Assignment of Adjustable Delay Buffers for Clock Skew Minimization in Multi-Voltage Mode Designs |
Author | *Kyoung-Hwan Lim, Taewhan Kim (Seoul National Univ., Republic of Korea) |
Page | pp. 503 - 508 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | On Applying Erroneous Clock Gating Conditions to Further Cut Down Power |
Author | *Tak-Kei Lam, Xiaoqing Yang, Wai-Chung Tang, Yu-Liang Wu (Chinese Univ. of Hong Kong, Hong Kong) |
Page | pp. 509 - 514 |
Detailed information (abstract, keywords, etc) |
Title | Low Power Discrete Voltage Assignment Under Clock Skew Scheduling |
Author | Li Li (Northwestern Univ., U.S.A.), Jian Sun (Fudan Univ., China), Yinghai Lu, *Hai Zhou (Northwestern Univ., U.S.A.), Xuan Zeng (Fudan Univ., China) |
Page | pp. 515 - 520 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | A Practical Method for Multi-domain Clock Skew Optimization |
Author | *Yanling Zhi (Fudan Univ., China), Hai Zhou (Northwestern Univ., U.S.A.), Xuan Zeng (Fudan Univ., China) |
Page | pp. 521 - 526 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Efficient Multi-Layer Obstacle-Avoiding Preferred Direction Rectilinear Steiner Tree Construction |
Author | *Jia-Ru Chuang, Jai-Ming Lin (National Cheng Kung Univ., Taiwan) |
Page | pp. 527 - 532 |
Detailed information (abstract, keywords, etc) |
Title | Cut-Demand Based Routing Resource Allocation and Consolidation for Routability Enhancement |
Author | *Fong-Yuan Chang (National Tsing Hua Univ., Taiwan), Sheng-Hsiung Chen (SpringSoft, Taiwan), Ren-Song Tsay, Wai-Kei Mak (National Tsing Hua Univ., Taiwan) |
Page | pp. 533 - 538 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Negotiation-Based Layer Assignment for Via Count and Via Overflow Minimization |
Author | *Wen-Hao Liu, Yih-Lang Li (National Chiao Tung Univ., Taiwan) |
Page | pp. 539 - 544 |
Detailed information (abstract, keywords, etc) |
Title | Wire Synthesizable Global Routing for Timing Closure |
Author | Michael Moffitt (IBM Corp., U.S.A.), *C. N. Sze (IBM Research, U.S.A.) |
Page | pp. 545 - 550 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) Biological Information Sensing Technologies for Medical, Health Care, and Wellness Applications |
Author | Masaharu Imai, Yoshinori Takeuchi, Keishi Sakanushi, Hirofumi Iwato (Osaka Univ., Japan) |
Page | pp. 551 - 555 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | (Invited Paper) Ultra-Low Power Microcontrollers for Portable, Wearable, and Implantable Medical Electronics |
Author | Srinivasa R. Sridhara (Texas Instruments, Inc., U.S.A.) |
Page | pp. 556 - 560 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | (Invited Paper) Human++: Wireless Autonomous Sensor Technology for Body Area Networks |
Author | Valer Pop, Ruben de Francisco, Hans Pflug, Juan Santana, Huib Visser, Ruud Vullers, Harmke de Groot, Bert Gyselinckx (IMEC, Netherlands) |
Page | pp. 561 - 566 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | (Invited Paper) Healthcare of an Organization: Using Wearable Sensors and Feedback System for Energizing Workers |
Author | Koji Ara, Tomoaki Akitomi, Nobuo Sato, Satomi Tsuji, Miki Hayakawa, Yoshihiro Wakisaka, Norio Ohkubo, Rieko Otsuka, Fumiko Beniyama, Norihiko Moriwaki, Kazuo Yano (Hitachi, Ltd., Japan) |
Page | pp. 567 - 572 |
Detailed information (abstract, keywords, etc) | |
Slides |
Friday, January 28, 2011 |
Title | (Keynote Address) Robust Systems: From Clouds to Nanotubes |
Author | Subhasish Mitra (Stanford Univ., U.S.A.) |
Detailed information (abstract, keywords, etc) |
Title | A Polynomial-Time Custom Instruction Identification Algorithm Based on Dynamic Programming |
Author | *Junwhan Ahn, Imyong Lee, Kiyoung Choi (Seoul National Univ., Republic of Korea) |
Page | pp. 573 - 578 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Exploring the Fidelity-Efficiency Design Space using Imprecise Arithmetic |
Author | *Jiawei Huang, John Lach (Univ. of Virginia, U.S.A.) |
Page | pp. 579 - 584 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Throughput Optimization for Latency-Insensitive System with Minimal Queue Insertion |
Author | Juinn-Dar Huang, *Yi-Hang Chen, Ya-Chien Ho (National Chiao Tung Univ., Taiwan) |
Page | pp. 585 - 590 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | A Fast and Effective Dynamic Trace-based Method for Analyzing Architectural Performance |
Author | *Yi-Siou Chen, Lih-Yih Chiou, Hsun-Hsiang Chang (National Cheng Kung Univ., Taiwan) |
Page | pp. 591 - 596 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Controlling NBTI Degradation during Static Burn-in Testing |
Author | *Ashutosh Chakraborty, David Z. Pan (Univ. of Texas, Austin, U.S.A.) |
Page | pp. 597 - 602 |
Detailed information (abstract, keywords, etc) |
Title | A Fine-Grained Technique of NBTI-Aware Voltage Scaling and Body Biasing for Standard Cell Based Designs |
Author | *Yongho Lee (Samsung Electronics, Republic of Korea), Taewhan Kim (Seoul National Univ., Republic of Korea) |
Page | pp. 603 - 608 |
Detailed information (abstract, keywords, etc) |
Title | NBTI-Aware Power Gating Design |
Author | Ming-Chao Lee, *Yu-Guang Chen, Ding-Kai Huang, Shih-Chieh Chang (National Tsing Hua Univ., Taiwan) |
Page | pp. 609 - 614 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Robust Power Gating Reactivation By Dynamic Wakeup Sequence Throttling |
Author | Tung-Yeh Wu, Shih-Hsin Hu, *Jacob A. Abraham (Univ. of Texas, Austin, U.S.A.) |
Page | pp. 615 - 620 |
Detailed information (abstract, keywords, etc) |
Title | Robust Clock Tree Synthesis with Timing Yield Optimization for 3D-ICs |
Author | *Jae-Seok Yang, Jiwoo Pak (Univ. of Texas, Austin, U.S.A.), Xin Zhao, Sung Kyu Lim (Georgia Tech, U.S.A.), David Z. Pan (Univ. of Texas, Austin, U.S.A.) |
Page | pp. 621 - 626 |
Detailed information (abstract, keywords, etc) |
Title | Track Routing Optimizing Timing and Yield |
Author | Xin Gao, *Luca Macchiarulo (Univ. of Hawaii, Manoa, U.S.A.) |
Page | pp. 627 - 632 |
Detailed information (abstract, keywords, etc) |
Title | Simultaneous Redundant Via Insertion and Line End Extension for Yield Optimization |
Author | Shing-Tung Lin (National Tsing Hua Univ., Taiwan), Kuang-Yao Lee (Taiwan Semiconductor Manufacturing Company, Taiwan), *Ting-Chi Wang (National Tsing Hua Univ., Taiwan), Cheng-Kok Koh (Purdue Univ., U.S.A.), Kai-Yuan Chao (Intel Corp., U.S.A.) |
Page | pp. 633 - 638 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Pruning-based Trace Signal Selection Algorithm |
Author | *Kang Zhao, Jinian Bian (Tsinghua Univ., China) |
Page | pp. 639 - 644 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | (Invited Paper) Temporal and Spatial Isolation in a Virtualization Layer for Multi-core Processor based Information Appliances |
Author | Tatsuo Nakajima, Yuki Kinebuchi, Hiromasa Shimada, Alexandre Courbot, Tsung-Han Lin (Waseda Univ., Japan) |
Page | pp. 645 - 652 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) Mathematical Limits of Parallel Computation for Embedded Systems |
Author | Jason Loew, Jesse Elwell, Dmitry Ponomarev, Patrick H. Madden (SUNY Binghamton Computer Science Department, U.S.A.) |
Page | pp. 653 - 660 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) An Enhanced Leakage-Aware Scheduler for Dynamically Reconfigurable FPGAs |
Author | Jen-Wei Hsieh (National Taiwan Univ. of Science and Tech., Taiwan), Yuan-Hao Chang (National Taipei Univ. of Tech., Taiwan), Wei-Li Lee (National Taiwan Univ. of Science and Tech., Taiwan) |
Page | pp. 661 - 667 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) Power Management Strategies in Data Transmission |
Author | Tiefei Zhang (Zhejiang Univ., China), Ying-Jheng Chen, Che-Wei Chang, Chuan-Yue Yang, Tei-Wei Kuo (National Taiwan Univ., Taiwan), Tianzhou Chen (Zhejiang Univ., China) |
Page | pp. 668 - 675 |
Detailed information (abstract, keywords, etc) |
Title | Robust Spatial Correlation Extraction with Limited Sample via L1-Norm Penalty |
Author | Mingzhi Gao, *Zuochang Ye, Dajie Zeng, Yan Wang, Zhiping Yu (Tsinghua Univ., China) |
Page | pp. 677 - 682 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Device-Parameter Estimation with On-chip Variation Sensors Considering Random Variability |
Author | *Ken-ichi Shinkai, Masanori Hashimoto (Osaka Univ., Japan) |
Page | pp. 683 - 688 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Accounting for Inherent Circuit Resilience and Process Variations in Analyzing Gate Oxide Reliability |
Author | Jianxin Fang, *Sachin S. Sapatnekar (Univ. of Minnesota, U.S.A.) |
Page | pp. 689 - 694 |
Detailed information (abstract, keywords, etc) |
Title | Variation-Tolerant and Self-Repair Design Methodology for Low Temperature Polycrystalline Silicon Liquid Crystal and Organic Light Emitting Diode Displays |
Author | *Chih-Hsiang Ho, Chao Lu, Debabrata Mohapatra, Kaushik Roy (Purdue Univ., U.S.A.) |
Page | pp. 695 - 700 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | A Physical-Location-Aware Fault Redistribution for Maximum IR-Drop Reduction |
Author | *Fu-Wei Chen, Shih-Liang Chen, Yung-Sheng Lin, TingTing Hwang (National Tsing Hua Univ., Taiwan) |
Page | pp. 701 - 706 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | On the Impact of Gate Oxide Degradation on SRAM Dynamic and Static Write-ability |
Author | *Vikas Chandra, Robert Aitken (ARM, U.S.A.) |
Page | pp. 707 - 712 |
Detailed information (abstract, keywords, etc) |
Title | A Self-Testing and Calibration Method for Embedded Successive Approximation Register ADC |
Author | Xuan-Lun Huang, Ping-Ying Kang (National Taiwan Univ., Taiwan), Hsiu-Ming Chang (Univ. of California, Santa Barbara, U.S.A.), *Jiun-Lang Huang (National Taiwan Univ., Taiwan), Yung-Fa Chou, Yung-Pin Lee, Ding-Ming Kwai, Cheng-Wen Wu (ITRI, Taiwan) |
Page | pp. 713 - 718 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | On-chip Dynamic Signal Sequence Slicing for Efficient Post-Silicon Debugging |
Author | *Yeonbok Lee, Takeshi Matsumoto, Masahiro Fujita (Univ. of Tokyo, Japan) |
Page | pp. 719 - 724 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | AVS-Aware Power-Gate Sizing for Maximum Performance and Power Efficiency of Power-Constrained Processors |
Author | Abhishek Sinkar, *Nam Sung Kim (Univ. of Wisconsin-Madison, U.S.A.) |
Page | pp. 725 - 730 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Energy/Reliability Trade-offs in Fault-Tolerant Event-Triggered Distributed Embedded Systems |
Author | *Junhe Gan (Tech. Univ. of Denmark, Denmark), Flavius Gruian (Lund Univ., Sweden), Paul Pop, Jan Madsen (Tech. Univ. of Denmark, Denmark) |
Page | pp. 731 - 736 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Profile Assisted Online System-Level Performance and Power Estimation for Dynamic Reconfigurable Embedded Systems |
Author | Jingqing Mu, *Roman Lysecky (Univ. of Arizona, U.S.A.) |
Page | pp. 737 - 742 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Battery-Aware Task Scheduling in Distributed Mobile Systems with Lifetime Constraint |
Author | Jiayin Li, *Meikang Qiu (Univ. of Kentucky, U.S.A.), Jian-wei Niu (Beihang Univ., China), Tianzhou Chen (Zhejiang Univ., China) |
Page | pp. 743 - 748 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) Advanced System LSIs for Home 3D System |
Author | Takao Suzuki (Panasonic Corp., Japan) |
Page | pp. 749 - 754 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | (Invited Paper) Development of Low Power and High Performance Application Processor (T6G) for Multimedia Mobile Applications |
Author | Yoshiyuki Kitasho, Yu Kikuchi, Takayoshi Shimazawa, Yasuo Ohara, Masafumi Takahashi, Yoshio Masubuchi, Yukihito Oowaki (Toshiba Corp. Semiconductor Company, Japan) |
Page | pp. 755 - 759 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | (Invited Paper) Design Constraint of Fine Grain Supply Voltage Control LSI |
Author | Atsuki Inoue (Fujitsu Labs., Japan) |
Page | pp. 760 - 765 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | (Invited Paper) FPGA Prototyping using Behavioral Synthesis for Improving Video Processing Algorithm and FHD TV SoC Design |
Author | Masaru Takahashi (Renesas Electronics Corp., Japan) |
Page | pp. 766 - 769 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | (Invited Paper) An RTL-to-GDS2 Design Methodology for Advanced System LSI |
Author | Nobuyuki Nishiguchi (STARC, Japan) |
Page | pp. 770 - 774 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | High Performance Lithographic Hotspot Detection using Hierarchically Refined Machine Learning |
Author | Duo Ding (Univ. of Texas, Austin, U.S.A.), Andres Torres, Fedor Pikus (Mentor Graphics Corp., U.S.A.), *David Pan (Univ. of Texas, Austin, U.S.A.) |
Page | pp. 775 - 780 |
Detailed information (abstract, keywords, etc) |
Title | Rapid Layout Pattern Classification |
Author | *Jen-Yi Wuu (Univ. of California, Santa Barbara, U.S.A.), Fedor G. Pikus, Andres Torres (Mentor Graphics Corp., U.S.A.), Malgorzata Marek-Sadowska (Univ. of California, Santa Barbara, U.S.A.) |
Page | pp. 781 - 786 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Mask Cost Reduction with Circuit Performance Consideration for Self-Aligned Double Patterning |
Author | Hongbo Zhang, Yuelin Du, *Martin D. F. Wong (Univ. of Illinois, Urbana-Champaign, U.S.A.), Kai-Yuan Chao (Intel Corp., U.S.A.) |
Page | pp. 787 - 792 |
Detailed information (abstract, keywords, etc) |
Title | Post-Routing Layer Assignment for Double Patterning |
Author | *Jian Sun (Fudan Univ., China), Yinghai Lu, Hai Zhou (Northwestern Univ., U.S.A.), Xuan Zeng (Fudan Univ., China) |
Page | pp. 793 - 798 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Fault Simulation and Test Generation for Clock Delay Faults |
Author | *Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi (Ehime Univ., Japan), Kewal K. Saluja (Univ. of Wisconsin-Madison, U.S.A.) |
Page | pp. 799 - 805 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Compression-Aware Capture Power Reduction for At-Speed Testing |
Author | *Jia Li (Tsinghua Univ., China), Qiang Xu (Chinese Univ. of Hong Kong, Hong Kong), Dong Xiang (Tsinghua Univ., China) |
Page | pp. 806 - 811 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Fault Diagnosis Aware ATE Assisted Test Response Compaction |
Author | Joseph Howard, *Sudhakar M Reddy (Univ. of Iowa, U.S.A.), Irith Pomeranz (Purdue Univ., U.S.A.), Bernd Becker (Univ. of Freiburg, Germany) |
Page | pp. 812 - 817 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Secure Scan Design Using Shift Register Equivalents against Differential Behavior Attack |
Author | *Hideo Fujiwara (NAIST, Japan), Katsuya Fujiwara, Hideo Tamamoto (Akita Univ., Japan) |
Page | pp. 818 - 823 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | An Efficient Algorithm of Adjustable Delay Buffer Insertion for Clock Skew Minimization in Multiple Dynamic Supply Voltage Designs |
Author | Kuan-Yu Lin, *Hong-Ting Lin, Tsung-Yi Ho (National Cheng Kung Univ., Taiwan) |
Page | pp. 825 - 830 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | An Integer Programming Placement Approach to FPGA Clock Power Reduction |
Author | *Alireza Rakhshanfar, Jason Anderson (Univ. of Toronto, Canada) |
Page | pp. 831 - 836 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Row-Based Area-Array I/O Design Planning in Concurrent Chip-Package Design Flow |
Author | Ren-Jie Lee, *Hung-Ming Chen (National Chiao Tung Univ., Taiwan) |
Page | pp. 837 - 842 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | A Provably Good Approximation Algorithm for Rectangle Escape Problem with Application to PCB Routing |
Author | Qiang Ma, Hui Kong, *Martin D. F. Wong (Univ. of Illinois, Urbana-Champaign, U.S.A.), Evangeline F. Y. Young (Chinese Univ. of Hong Kong, Hong Kong) |
Page | pp. 843 - 848 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | (Panel Discussion) Advanced Packaging and 3D Technologies |
Author | Organizer: Yoshio Masubuchi (Toshiba, Japan), Moderator: Kenichi Osada (Hitachi, Japan), Panelists: Geert Van der Plas (IMEC, Belgium), Hirokazu Ezawa (Toshiba, Japan), Yasumitsu Orii (IBM, Japan), Yoichi Hiruta (J-Devices, Japan), Chris Cheung (Cadence Design Systems, U.S.A.) |
Detailed information (abstract, keywords, etc) | |
Slides |