The 22nd Asia and South Pacific Design Automation Conference
Technical Program

Remark: The presenter of each paper is marked with "*".

Technical Program: Session Schedule SIMPLE version DETAILED version with abstract

Author Index: HERE

Session Schedule

Tuesday, January 17, 2017

Room 103	Room 102	Room 104	Room 105
1K (International Conference Room) Opening & Keynote I 8:30 - 10:35
Coffee Break 10:35 - 11:05
1S University Design Contest 11:05 - 12:20	1A Design Assurance and Reliability 11:05 - 12:20	1B New Frontiers of Hardware Accelerator Synthesis 11:05 - 12:20	1C Analysis Techniques for Reliability and Manufacturability 11:05 - 12:20
Lunch Break 12:20 - 13:50
2S (Special Session) Neuromorphic Computing and Low-Power Image Recognition 13:50 - 15:30	2A System-level Techniques for Energy and Performance Optimization 13:50 - 15:30	2B Pushing the Limits of Logic Synthesis 13:50 - 15:30	2C Design Techniques for Reliability Enhancement 13:50 - 15:30
Coffee Break 15:30 - 15:50
3S (Special Session) Let's Secure the Physics of Cyber-Physical Systems 15:50 - 17:30	3A Novel Techniques to Improve the Simulation Performance 15:50 - 17:30	3B Formal and Informal Verification 15:50 - 17:30	3C Pursuing System to Circuit Level Optimality in Timing and Power Integrity 15:50 - 17:30

Wednesday, January 18, 2017

Room 103	Room 102	Room 104	Room 105
2K (International Conference Room) Keynote II 9:00 - 9:50
Coffee Break 9:50 - 10:15
4S (Special Session) Emerging Technologies for Biomedical Applications: Artificial Vision Systems and Brain Machine Interface 10:15 - 12:15	4A Power and Thermal Management 10:15 - 12:20	4B Emerging Topics in Hardware Security 10:15 - 12:20	4C Manufacturability and Emerging Techniques 10:15 - 12:20
Lunch Break 12:20 - 13:50
5S (Designers' Forum) Advanced Devices and Networks for IoT Applications 13:50 - 15:30	5A Approximate Computation for Energy Efficiency 13:50 - 15:30	5B Advance Test and Fault Tolerant Technologies 13:50 - 15:30	5C Advanced Placement and Routing Techniques 13:50 - 15:30
Coffee Break 15:30 - 15:50
6S (Designers' Forum) Panel Discussion: What is future AI we will create ? - "Doraemon" or "Terminator" ? - 15:50 - 17:30	6A Recent Advances in Circuit Simulation and Optimization 15:50 - 17:30	6B Application-Aware Embedded Architecture Design 15:50 - 17:30	6C Advances in Microfluidic Biochips 15:50 - 17:30
Banquet (Convention Hall A) 18:00 - 20:00

Thursday, January 19, 2017

Room 103	Room 102	Room 104	Room 105
3K (International Conference Room) Keynote III 9:00 - 9:50
Coffee Break 9:50 - 10:15
7S (Special Session) When Backend Meets Frontend: Cross-Layer Design & Optimization for System Robustness 10:15 - 12:15	7A NVM/Flash: From Advanced Storage Design to Emerging Applications 10:15 - 12:20	7B Hardware Diversity and Hardware Trojan 10:15 - 12:20	7C Hardware Accelerator for Emerging Applications 10:15 - 12:20
Lunch Break 12:20 - 13:50
8S (Designers' Forum) Advanced Automotive Security 13:50 - 15:30	8A Scheduling, Resource Management, and Simulation for Multi-Core Systems 13:50 - 15:30	8B Machine Learning: Acceleration and Application 13:50 - 15:30	8C Design Automation and Modeling for Emerging Technologies 13:50 - 15:30
Coffee Break 15:30 - 15:50
9S (Designers' Forum) Advanced Image Sensing and Processing 15:50 - 17:30	9A New Directions in Networks on Chip 15:50 - 17:30	9B Memory Architecture: Now and Future 15:50 - 17:30	9C Intelligent Computing with Memristor Technologies 15:50 - 17:30

List of papers

Remark: The presenter of each paper is marked with "*".

Tuesday, January 17, 2017

Session 1K Opening & Keynote I
Time: 8:30 - 10:35 Tuesday, January 17, 2017
Location: International Conference Room

1K-1

Title	(Keynote Address) In Memory of Edward J. McCluskey: The Next Wave of Pioneering Innovations
Author	Organizers/Chairs: Subhasish Mitra (Stanford Univ., U.S.A.), Deming Chen (Univ. of Illinois, Urbana-Champaign, U.S.A.)
Page	p. 1
Detailed information (abstract, keywords, etc)

1K-2

Title	(Keynote Address) Heterogeneous Integration of X-tronics: Design Automation and Education
Author	K.-T. Tim Cheng (Hong Kong Univ. of Science and Tech., Hong Kong)
Page	p. 2
Detailed information (abstract, keywords, etc)

1K-3

Title	(Keynote Address) Electronics for the Human Body
Author	John Rogers (Northwestern Univ., U.S.A.)
Page	p. 3
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1K-4

Title	(Keynote Address) Design of Society: Beyond Digital System Design
Author	Hiroto Yasuura (Kyushu Univ., Japan)
Page	p. 4
Detailed information (abstract, keywords, etc)

Session 1S University Design Contest
Time: 11:05 - 12:20 Tuesday, January 17, 2017
Location: Room 103
Chairs: Noriyuki Miura (Kobe Univ., Japan), Hiroyuki Ito (Tokyo Inst. of Tech., Japan)

1S-1 (Time: 11:05 - 11:08)

Title	W-Band Ultra-High Data-Rate 65nm CMOS Wireless Transceiver
Author	*Korkut Kaan Tokgoz, Shotaro Maki, Seitarou Kawai, Noriaki Nagashima (Tokyo Inst. of Tech., Japan), Yoichi Kawano, Toshihide Suzuki, Taisuke Iwai (Fujitsu Labs., Japan), Kenichi Okada, Akira Matsuzawa (Tokyo Inst. of Tech., Japan)
Page	pp. 5 - 6
Detailed information (abstract, keywords, etc)
Slides

1S-2 (Time: 11:08 - 11:11)

Title	An Image Sensor/Processor 3D Stacked Module Featuring ThruChip Interfaces
Author	*Masayuki Ikebe, Tetsuya Asai, Masafumi Mori, Toshiyuki Itou, Daisuke Uchida (Hokkaido Univ., Japan), Yasuhiro Take, Tadahiro Kuroda (Keio Univ., Japan), Masato Motomura (Hokkaido Univ., Japan)
Page	pp. 7 - 8
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Slides

1S-3 (Time: 11:11 - 11:14)

Title	A 686Mbps 1.85mm² Near-Optimal Symbol Detector for Spatial Modulation MIMO Systems in 0.18μm CMOS
Author	*Hye-Yeon Yoon, Gwang-Ho Lee, Tae-Hwan Kim (Korea Aerospace Univ., Republic of Korea)
Page	pp. 9 - 10
Detailed information (abstract, keywords, etc)
Slides

1S-4 (Time: 11:14 - 11:17)

Title	A Scalable Time-Domain Biosensor Array Using Logarithmic Cyclic Time-Attenuation-Based TDC for High-Resolution and Large-Scale Bio-Imaging
Author	Kei Ikeda, Atsuki Kobayashi, Kazuo Nakazato (Nagoya Univ., Japan), *Kiichi Niitsu (Nagoya Univ., JST PRESTO, Japan)
Page	pp. 11 - 12
Detailed information (abstract, keywords, etc)
Slides

1S-5 (Time: 11:17 - 11:20)

Title	An HDL-Synthesized Injection-Locked PLL Using LC-Based DCO for On-chip Clock Generation
Author	*Dongsheng Yang, Wei Deng, Bangan Liu, Aravind Tharayil Narayanan, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa (Tokyo Inst. of Tech., Japan)
Page	pp. 13 - 14
Detailed information (abstract, keywords, etc)
Slides

1S-6 (Time: 11:20 - 11:23)

Title	A 14bit 80kSPS Non-Binary Cyclic ADC without High Accuracy Analog Components
Author	*Yuki Watanabe, Hayato Narita, Hiroyuki Tsuchiya (Tokyo City Univ., Japan), Tatsuji Matsuura (Tokyo Univ. of Science, Japan), Hao San, Masao Hotta (Tokyo City Univ., Japan)
Page	pp. 15 - 16
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Slides

1S-7 (Time: 11:23 - 11:26)

Title	Non-Binary Cyclic ADC with Correlated Level Shifting Technique
Author	*Hiroyuki Tsuchiya, Asato Uchiyama, Yuta Misima, Yuki Watanabe, Hao San, Masao Hotta (Tokyo City Univ., Japan), Tatsuji Matsuura (Tokyo Univ. of Science, Japan)
Page	pp. 17 - 18
Detailed information (abstract, keywords, etc)
Slides

1S-8 (Time: 11:26 - 11:29)

Title	A Current-Integration-Based CMOS Amperometric Sensor with 1.2 μm × 2.05 μm Electroless-Plated Microelectrode Array for High-Sensitivity Bacteria Counting
Author	*Kohei Gamo, Kazuo Nakazato (Nagoya Univ., Japan), Kiichi Niitsu (Nagoya Univ., JST PRESTO, Japan)
Page	pp. 19 - 20
Detailed information (abstract, keywords, etc)
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1S-9 (Time: 11:29 - 11:32)

Title	A Real-time 17-Scale Object Detection Accelerator with Adaptive 2000-Stage Classification in 65nm CMOS
Author	*Minkyu Kim, Abinash Mohanty, Deepak Kadetotad (Arizona State Univ., U.S.A.), Naveen Suda (ARM, U.S.A.), Luning Wei (Zhejiang Univ., China), Pooja Saseendran (Arizona State Univ., U.S.A.), Xiaofei He (Zhejiang Univ., China), Yu Cao, Jae-sun Seo (Arizona State Univ., U.S.A.)
Page	pp. 21 - 22
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Slides

1S-10 (Time: 11:32 - 11:35)

Title	A 15 x 15 SPAD Array Sensor with Breakdown-Pixel-Extraction Architecture for Efficient Data Readout
Author	*Xiao Yang, Hongbo Zhu, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada (Univ. of Tokyo, Japan)
Page	pp. 23 - 24
Detailed information (abstract, keywords, etc)
Slides

1S-11 (Time: 11:35 - 11:38)

Title	Design of an Energy-Autonomous Bio-Sensing System Using a Biofuel Cell and 0.19V 53µW Integrated Supply-Sensing Sensor with a Supply-Insensitive Temperature Sensor and Inductive-Coupling Transmitter
Author	*Atsuki Kobayashi, Kei Ikeda (Nagoya Univ., Japan), Yudai Ogawa, Matsuhiko Nishizawa (Tohoku Univ., Japan), Kazuo Nakazato (Nagoya Univ., Japan), Kiichi Niitsu (Nagoya Univ., JST PRESTO, Japan)
Page	pp. 25 - 26
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Slides

1S-12 (Time: 11:38 - 11:41)

Title	A 13.56MHz CMOS Active Diode Full-Wave Rectifier Achieving ZVS with Voltage-Time-Conversion Delay-Locked Loop for Wireless Power Transmission
Author	Keita Yogosawa, Hideki Shinohara, *Kousuke Miyaji (Shinshu Univ., Japan)
Page	pp. 27 - 28
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Slides

1S-13 (Time: 11:41 - 11:44)

Title	CMOS-on-Quartz Pulse Generator for Low Power Applications
Author	*Parit Kanjanavirojkul, Nguyen Ngoc Mai-Khanh, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada (Univ. of Tokyo, Japan)
Page	pp. 29 - 30
Detailed information (abstract, keywords, etc)
Slides

1S-14 (Time: 11:44 - 11:47)

Title	A 13.56 MHz On/Off Delay-Compensated Fully-Integrated Active Rectifier for Biomedical Wireless Power Transfer Systems
Author	*Lin Cheng, Wing-Hung Ki, Tak-Sang Yim (Hong Kong Univ. of Science and Tech., Hong Kong)
Page	pp. 31 - 32
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1S-15 (Time: 11:47 - 11:50)

Title	A Wireless Power Receiver with a 3-Level Reconfigurable Resonant Regulating Rectifier for Mobile-Charging Applications
Author	*Lin Cheng, Wing-Hung Ki, Chi-Ying Tsui (Hong Kong Univ. of Science and Tech., Hong Kong)
Page	pp. 33 - 34
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1S-16 (Time: 11:50 - 11:53)

Title	Sub-1-µs Start-up Time, 32-MHz Relaxation Oscillator for Low-Power Intermittent VLSI Systems
Author	*Hiroki Asano, Tetsuya Hirose, Taro Miyoshi, Keishi Tsubaki, Toshihiro Ozaki, Nobutaka Kuroki, Masahiro Numa (Kobe Univ., Japan)
Page	pp. 35 - 36
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Slides

1S-17 (Time: 11:53 - 11:56)

Title	A 19-μA Metabolic Equivalents Monitoring SoC Using Adaptive Sampling
Author	*Mio Tsukahara, Shintaro Izumi, Motofumi Nakanishi, Hiroshi Kawaguchi (Kobe Univ., Japan), Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori (Rohm, Japan), Masahiko Yoshimoto (Kobe Univ., Japan)
Page	pp. 37 - 38
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1S-18 (Time: 11:56 - 11:59)

Title	An FPGA-Compatible PLL-Based Sensor against Fault Injection Attack
Author	Wei He, Jakub Breier, *Shivam Bhasin (Nanyang Technological Univ., Singapore), Noriyuki Miura, Makoto Nagata (Kobe Univ., Japan)
Page	pp. 39 - 40
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Slides

1S-19 (Time: 11:59 - 12:02)

Title	Variability Mapping at Runtime Using the PAnDA Multi-reconfigurable Architecture
Author	*Simon Bale (Univ. of York, U.K.), James Walker (Univ. of Hull, U.K.), Martin Trefzer, Andy Tyrrell (Univ. of York, U.K.)
Page	pp. 41 - 42
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Slides

1S-20 (Time: 12:02 - 12:05)

Title	Design of High-Frequency Piezoelectric Resonator-Based Cascaded Fractional-N PLL with Sub-ppb-Order Channel Adjusting Technique
Author	*Yosuke Ishikawa, Sho Ikeda, Hiroyuki Ito (Tokyo Inst. of Tech., Japan), Akifumi Kasamatsu (NICT, Japan), Takayoshi Obara, Naoki Noguchi, Koji Kamisuki, Yao Jiyang (Tokyo Inst. of Tech., Japan), Shinsuke Hara, Ruibing Dong (NICT, Japan), Shiro Dosho, Noboru Ishihara, Kazuya Masu (Tokyo Inst. of Tech., Japan)
Page	pp. 43 - 44
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Session 1A Design Assurance and Reliability
Time: 11:05 - 12:20 Tuesday, January 17, 2017
Location: Room 102
Chairs: Chih-Tsun Huang (National Tsing Hua Univ., Taiwan), Franco Fummi (Univ. of Verona, Italy)

1A-1 (Time: 11:05 - 11:30)

Title	AGARSoC: Automated Test and Coverage-Model Generation for Verification of Accelerator-Rich SoCs
Author	Biruk Mammo, *Doowon Lee, Harrison Davis, Yijun Hou, Valeria Bertacco (Univ. of Michigan, U.S.A.)
Page	pp. 45 - 50
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1A-2 (Time: 11:30 - 11:55)

Title	Feature Extraction from Design Documents to Enable Rule Learning for Improving Assertion Coverage
Author	*Kuo-Kai Hsieh, Sebastian Siatkowski, Li-Chung Wang (Univ. of California, Santa Barbara, U.S.A.), Wen Chen, Jayanta Bhadra (NXP Semiconductors, U.S.A.)
Page	pp. 51 - 56
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1A-3 (Time: 11:55 - 12:20)

Title	Trust is good, Control is better: Hardware-based Instruction-Replacement for Reliable Processor-IPs
Author	*Kenneth Schmitz, Arun Chandrasekharan, Jonas Gomes Filho, Daniel Große, Rolf Drechsler (Univ. of Bremen, Germany)
Page	pp. 57 - 62
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Session 1B New Frontiers of Hardware Accelerator Synthesis
Time: 11:05 - 12:20 Tuesday, January 17, 2017
Location: Room 104
Chairs: Seiya Shibata (NEC, Japan), Takefumi Miyoshi (e-trees.Japan)

1B-1 (Time: 11:05 - 11:30)

Title	Efficient Floating Point Precision Tuning for Approximate Computing
Author	*Nhut-Minh Ho, Elavarasi Manogaran, Weng-Fai Wong (National Univ. of Singapore, Singapore), Asha Anoosheh (Univ. of California, Berkeley, U.S.A.)
Page	pp. 63 - 68
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Slides

1B-2 (Time: 11:30 - 11:55)

Title	Area-Constrained Technology Mapping for In-Memory Computing Using ReRAM Devices
Author	Debjyoti Bhattacharjee, Arvind Easwaran, *Anupam Chattopadhyay (Nanyang Technological Univ., Singapore)
Page	pp. 69 - 74
Detailed information (abstract, keywords, etc)

1B-3 (Time: 11:55 - 12:20)

Title	Tessellating Memory Space for Parallel Access
Author	*Juan Escondido, Mingjie Lin (UCF, U.S.A.)
Page	pp. 75 - 80
Detailed information (abstract, keywords, etc)

Session 1C Analysis Techniques for Reliability and Manufacturability
Time: 11:05 - 12:20 Tuesday, January 17, 2017
Location: Room 105
Chairs: Shao-Yun Fang (National Taiwan Univ. of Science and Tech., Taiwan), Song Chen (Univ. of Science and Tech. of China, China)

1C-1 (Time: 11:05 - 11:30)

Title	Lithography Hotspot Detection by Two-stage Cascade Classifier Using Histogram of Oriented Light Propagation
Author	*Yoichi Tomioka (Univ. of Aizu, Japan), Tetsuaki Matsunawa, Chikaaki Kodama, Shigeki Nojima (Toshiba, Japan)
Page	pp. 81 - 86
Detailed information (abstract, keywords, etc)
Slides

1C-2 (Time: 11:30 - 11:55)

Title	Reliability Analysis of Memories suffering MBUs for the Effect of Negative Bias Temperature Instability
Author	*Shanshan Liu, Liyi Xiao, Xuebing Cao, Zhigang Mao (Harbin Inst. of Tech., China)
Page	pp. 87 - 92
Detailed information (abstract, keywords, etc)
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1C-3 (Time: 11:55 - 12:20)

Title	Efficient Circuit Failure Probability Calculation along Product Lifetime Considering Device Aging
Author	*Hiromitsu Awano, Masayuki Hiromoto, Takashi Sato (Kyoto Univ., Japan)
Page	pp. 93 - 98
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Session 2S (Special Session) Neuromorphic Computing and Low-Power Image Recognition
Time: 13:50 - 15:30 Tuesday, January 17, 2017
Location: Room 103
Organizers/Chairs: Yiran Chen (Univ. of Pittsburgh, U.S.A.), Bo Yuan (City Univ. of New York, U.S.A.), Yung-Hsiang Lu (Purdue Univ., U.S.A.), Ying Wang (Chinese Academy of Sciences, China)

2S-1 (Time: 13:50 - 14:15)

Title	(Invited Paper) Low-Power Image Recognition Challenge
Author	*Kent Gauen, Rohit Rangan, Anup Mohan, Yung-Hsiang Lu (Purdue Univ., U.S.A.), Wei Liu, Alexander C. Berg (Univ. of North Carolina, U.S.A.)
Page	pp. 99 - 104
Detailed information (abstract, keywords, etc)
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2S-2 (Time: 14:15 - 14:40)

Title	(Invited Paper) CNN-based Object Detection Solutions for Embedded Heterogeneous Multi-core SoCs
Author	Cheng Wang, *Ying Wang, Yinhe Han, Lili Song, Zhenyu Quan, Jiajun Li, Xiaowei Li (Chinese Academy of Sciences, China)
Page	pp. 105 - 110
Detailed information (abstract, keywords, etc)

2S-3 (Time: 14:40 - 15:05)

Title	(Invited Paper) Low-Power Neuromorphic Speech Recognition Engine with Coarse-Grain Sparsity
Author	Shihui Yin, Deepak Kadetotad (Arizona State Univ., U.S.A.), Bonan Yan, Chang Song, Yiran Chen (Univ. of Pittsburgh, U.S.A.), Chaitali Chakrabarti, *Jae-sun Seo (Arizona State Univ., U.S.A.)
Page	pp. 111 - 114
Detailed information (abstract, keywords, etc)

2S-4 (Time: 15:05 - 15:30)

Title	(Invited Paper) Towards Acceleration of Deep Convolutional Neural Networks Using Stochastic Computing
Author	Ji Li (Univ. of Southern California, U.S.A.), Ao Ren, Zhe Li, Caiwen Ding (Syracuse Univ., U.S.A.), Bo Yuan (City Univ. of New York, U.S.A.), Qinru Qiu, *Yanzhi Wang (Syracuse Univ., U.S.A.)
Page	pp. 115 - 120
Detailed information (abstract, keywords, etc)
Slides

Session 2A System-level Techniques for Energy and Performance Optimization
Time: 13:50 - 15:30 Tuesday, January 17, 2017
Location: Room 102
Chairs: Liang Shi (Chongqing Univ., China), Takatsugu Ono (Kyushu Univ., Japan)

2A-1 (Time: 13:50 - 14:15)

Title	Enabling Fast Preemption via Dual-Kernel Support on GPUs
Author	Li-Wei Shieh (National Taiwan Univ., Taiwan), *Kun-Chih Chen (National Sun Yat-sen Univ., Taiwan), Hsueh-Chun Fu, Po-Han Wang, Chia-Lin Yang (National Taiwan Univ., Taiwan)
Page	pp. 121 - 126
Detailed information (abstract, keywords, etc)
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2A-2 (Time: 14:15 - 14:40)

Title	Efficient Mapping of CDFG onto Coarse-Grained Reconfigurable Array Architectures
Author	*Satyajit Das, Kevin Martin, Philippe Coussy (Univ. of South Brittany, France), Davide Rossi, Luca Benini (Univ. of Bologna, Italy)
Page	pp. 127 - 132
Detailed information (abstract, keywords, etc)
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2A-3 (Time: 14:40 - 15:05)

Title	Timing Window Wiper : A New Scheme for Reducing Refresh Power of DRAM
Author	*Ho Hyun Shin, Hyeokjun Seo, Byunghoon Lee, Jeongbin Kim, Eui-Young Chung (Yonsei Univ., Republic of Korea)
Page	pp. 133 - 138
Detailed information (abstract, keywords, etc)
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2A-4 (Time: 15:05 - 15:30)

Title	On Efficient Message Passing in Energy Harvesting Based Distributed System
Author	*Ye Tian, Qiang Xu (Chinese Univ. of Hong Kong, Hong Kong), Jason Xue (City Univ. of Hong Kong, Hong Kong)
Page	pp. 139 - 144
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Session 2B Pushing the Limits of Logic Synthesis
Time: 13:50 - 15:30 Tuesday, January 17, 2017
Location: Room 104
Chairs: Shouyi Yin (Tsinghua Univ., China), Shinobu Nagayama (Hiroshima City Univ., Japan)

2B-1 (Time: 13:50 - 14:15)

Title	Fast Extract with Cube Hashing
Author	*Bruno Schmitt (UFRGS, Brazil), Alan Mishchenko (UC Berkeley, U.S.A.), Victor Kravets (IBM, U.S.A.), Robert Brayton (UC Berkeley, U.S.A.), André Reis (UFRGS, Brazil)
Page	pp. 145 - 150
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2B-2 (Time: 14:15 - 14:40)

Title	A Novel Basis for Logic Rewriting
Author	*Winston Haaswijk, Mathias Soeken (EPFL, Switzerland), Luca Amarú (Synopsys, U.S.A.), Pierre-Emmanuel Gaillardon (Univ. of Utah, U.S.A.), Giovanni De Micheli (EPFL, Switzerland)
Page	pp. 151 - 156
Detailed information (abstract, keywords, etc)

2B-3 (Time: 14:40 - 15:05)

Title	Multi-level Logic Benchmarks: An Exactness Study
Author	*Luca Amaru (Synopsys, U.S.A.), Mathias Soeken, Winston Haaswijk, Eleonora Testa (EPFL, Switzerland), Patrick Vuillod, Jiong Luo (Synopsys, U.S.A.), Pierre-Emmanuel Gaillardon (Univ. of Utah, U.S.A.), Giovanni De Micheli (EPFL, Switzerland)
Page	pp. 157 - 162
Detailed information (abstract, keywords, etc)
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2B-4 (Time: 15:05 - 15:30)

Title	Approximate Logic Synthesis for FPGA by Wire Removal and Local Function Change
Author	*Yi Wu, Chuyu Shen, Yi Jia, Weikang Qian (Shanghai Jiao Tong Univ., China)
Page	pp. 163 - 169
Detailed information (abstract, keywords, etc)
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Session 2C Design Techniques for Reliability Enhancement
Time: 13:50 - 15:30 Tuesday, January 17, 2017
Location: Room 105
Chairs: Yukihide Kohira (Aizu Univ., Japan), Tetsuaki Matsunawa (Toshiba, Japan)

2C-1 (Time: 13:50 - 14:15)

Title	Guiding Template-aware Routing Considering Redundant Via Insertion for Directed Self-Assembly
Author	Kun-Lin Lin, *Shao-Yun Fang (National Taiwan Univ. of Science and Tech., Taiwan)
Page	pp. 170 - 175
Detailed information (abstract, keywords, etc)
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2C-2 (Time: 14:15 - 14:40)

Title	Workload-aware Static Aging Monitoring of Timing-critical Flip-flops
Author	*Arunkumar Vijayan, Saman Kiamehr, Fabian Oboril (Karlsruhe Inst. of Tech., Germany), Krishnendu Chakrabarty (Duke Univ., U.S.A.), Mehdi Tahoori (Karlsruhe Inst. of Tech., Germany)
Page	pp. 176 - 181
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2C-3 (Time: 14:40 - 15:05)

Title	Enhancing Robustness of Sequential Circuits Using Application-specific Knowledge and Formal Methods
Author	*Sebastian Huhn (Univ. of Bremen, Germany), Stefan Frehse (DFKI GmbH Bremen, Germany), Robert Wille (Johannes Kepler Univ. Linz, Austria), Rolf Drechsler (Univ. of Bremen, Germany)
Page	pp. 182 - 187
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2C-4 (Time: 15:05 - 15:30)

Title	WIPE: Wearout Informed Pattern Elimination to Improve the Endurance of NVM-based Caches
Author	*Sina Asadi, Amir Mahdi Hosseini Monazzah, Hamed Farbeh, Seyed Ghassem Miremadi (Sharif Univ. of Tech., Iran)
Page	pp. 188 - 193
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Session 3S (Special Session) Let's Secure the Physics of Cyber-Physical Systems
Time: 15:50 - 17:30 Tuesday, January 17, 2017
Location: Room 103
Organizers/Chairs: Mohammad Al Faruque (Univ. of California Irvine, U.S.A.), Anupam Chattopadhyay (Nanyang Technological Univ., Singapore), Francesco Regazzoni (ALaRI - USI, Switzerland)

3S-1 (Time: 15:55 - 16:25)

Title	(Invited Paper) Securing the Hardware of Cyber-Physical Systems
Author	*Francesco Regazzoni (ALaRI - USI, Switzerland), Ilia Polian (Univ. of Passau, Germany)
Page	pp. 194 - 199
Detailed information (abstract, keywords, etc)

3S-2 (Time: 16:25 - 16:55)

Title	(Invited Paper) Cross-Domain Security of Cyber-Physical Systems
Author	Sujit Rokka Chhetri, Jiang Wan, *Mohammad Al Faruque (Univ. of California Irvine, U.S.A.)
Page	pp. 200 - 205
Detailed information (abstract, keywords, etc)
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3S-3 (Time: 16:55 - 17:25)

Title	(Invited Paper) A Systematic Security Analysis of Real-Time Cyber-Physical Systems
Author	Arvind Easwaran, *Anupam Chattopadhyay, Shivam Bhasin (Nanyang Technological Univ., Singapore)
Page	pp. 206 - 213
Detailed information (abstract, keywords, etc)

Session 3A Novel Techniques to Improve the Simulation Performance
Time: 15:50 - 17:30 Tuesday, January 17, 2017
Location: Room 102
Chairs: Ing-Jer Huang (National Sun Yat-sen Univ., Taiwan), Masashi Tawada (Waseda Univ., Japan)

3A-1 (Time: 15:50 - 16:15)

Title	Automated Generation of Dynamic Binary Translators for Instruction Set Simulation
Author	*Katsumi Okuda, Minoru Yoshida, Haruhiko Takeyama, Minoru Nakamura (Mitsubishi Electric, Japan)
Page	pp. 214 - 219
Detailed information (abstract, keywords, etc)
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3A-2 (Time: 16:15 - 16:40)

Title	Loop Aware IR-Level Annotation Framework for Performance Estimation in Native Simulation
Author	*Omayma Matoussi, Frédéric Pétrot (Laboratoire TIMA, Univ. Grenoble Alpes, France)
Page	pp. 220 - 225
Detailed information (abstract, keywords, etc)
Slides

3A-3 (Time: 16:40 - 17:05)

Title	Hybrid Analysis of SystemC Models for Fast and Accurate Parallel Simulation
Author	*Tim Schmidt, Guantao Liu, Rainer Dömer (Univ. of California, Irvine, U.S.A.)
Page	pp. 226 - 231
Detailed information (abstract, keywords, etc)
Slides

3A-4 (Time: 17:05 - 17:30)

Title	Virtual Prototyping of Smart Systems through Automatic Abstraction and Mixed-Signal Scheduling
Author	Michele Lora, Enrico Fraccaroli, *Franco Fummi (Univ. of Verona, Italy)
Page	pp. 232 - 237
Detailed information (abstract, keywords, etc)
Slides

Session 3B Formal and Informal Verification
Time: 15:50 - 17:30 Tuesday, January 17, 2017
Location: Room 104
Chairs: Jason Verley (Sandia National Laboratory, U.S.A.), Rajit Manohar (Cornell Univ., U.S.A.)

3B-1 (Time: 15:50 - 16:15)

Title	Efficient Parallel Verification of Galois Field Multipliers
Author	*Cunxi Yu, Maciej Ciesielski (Univ. of Massachusetts, Amherst, U.S.A.)
Page	pp. 238 - 243
Detailed information (abstract, keywords, etc)
Slides

3B-2 (Time: 16:15 - 16:40)

Title	Property Mining Using Dynamic Dependency Graphs
Author	*Jan Malburg (German Aerospace Center, Germany), Tino Flenker (Univ. of Bremen, Germany), Görschwin Fey (German Aerospace Center, Germany)
Page	pp. 244 - 250
Detailed information (abstract, keywords, etc)
Slides

3B-3 (Time: 16:40 - 17:05)

Title	CEGAR-Based EF Synthesis of Boolean Functions with an Application to Circuit Rectification
Author	*Heinz Riener (German Aerospace Center, Germany), Rüdiger Ehlers (Univ. Bremen, Germany), Goerschwin Fey (German Aerospace Center, Germany)
Page	pp. 251 - 256
Detailed information (abstract, keywords, etc)
Slides

3B-4 (Time: 17:05 - 17:30)

Title	An Extensible Perceptron Framework for Revision RTL Debug Automation
Author	*John Adler, Ryan Berryhill, Andreas Veneris (Univ. of Toronto, Canada)
Page	pp. 257 - 262
Detailed information (abstract, keywords, etc)
Slides

Session 3C Pursuing System to Circuit Level Optimality in Timing and Power Integrity
Time: 15:50 - 17:30 Tuesday, January 17, 2017
Location: Room 105
Chairs: Takashi Sato (Kyoto Univ., Japan), Sheldon Tan (Univ. of California, Riverside, U.S.A.)

3C-1 (Time: 15:50 - 16:15)

Title	Algorithm for Synthesis and Exploration of Clock Spines
Author	*Youngchan Kim, Taewhan Kim (Seoul National Univ., Republic of Korea)
Page	pp. 263 - 268
Detailed information (abstract, keywords, etc)
Slides

3C-2 (Time: 16:15 - 16:40)

Title	Yield-Driven Redundant Power Bump Assignment for Power Network Robustness
Author	Yu-Min Lee, Chi-Han Lee, *Yan-Cheng Zhu (National Chiao Tung Univ., Taiwan)
Page	pp. 269 - 274
Detailed information (abstract, keywords, etc)

3C-3 (Time: 16:40 - 17:05)

Title	A Tighter Recursive Calculus to Compute the Worst Case Traversal Time of Real-Time Traffic over NoCs
Author	*Meng Liu, Matthias Becker, Moris Behnam, Thomas Nolte (Mälardalen Univ., Sweden)
Page	pp. 275 - 282
Detailed information (abstract, keywords, etc)
Slides

3C-4 (Time: 17:05 - 17:30)

Title	An Efficient Homotopy-Based Poincaré-Lindstedt Method for the Periodic Steady-State Analysis of Nonlinear Autonomous Oscillators
Author	Zhongming Chen, *Kim Batselier (Univ. of Hong Kong, Hong Kong), Haotian Liu (Cadence Design Systems, U.S.A.), Ngai Wong (Univ. of Hong Kong, Hong Kong)
Page	pp. 283 - 288
Detailed information (abstract, keywords, etc)
Slides

Wednesday, January 18, 2017

Session 2K Keynote II
Time: 9:00 - 9:50 Wednesday, January 18, 2017
Location: International Conference Room
Chair: Masaharu Imai (Osaka Univ., Japan)

2K-1 (Time: 9:00 - 9:50)

Title	(Keynote Address) Emerging Medical Technologies for Interfacing the Brain: From Deep Brain Stimulation to Brain Computer Interfaces
Author	Napoleon Torres-Martinez (CEA LETI, France)
Page	p. 289
Detailed information (abstract, keywords, etc)

Session 4S (Special Session) Emerging Technologies for Biomedical Applications: Artificial Vision Systems and Brain Machine Interface
Time: 10:15 - 12:15 Wednesday, January 18, 2017
Location: Room 103
Organizer: Masaharu Imai (Osaka Univ., Japan), Moderator: Yoshinori Takeuchi (Osaka Univ., Japan)

4S-1 (Time: 10:15 - 10:45)

Title	(Invited Paper) Smart Electrode - Toward a Retinal Stimulator with the Large Number of Electrodes -
Author	*Jun Ohta (NAIST, Japan)
Page	p. 290
Detailed information (abstract, keywords, etc)

4S-2 (Time: 10:45 - 11:15)

Title	(Invited Paper) Strategic Circuits for Neuromodulation of the Visual System
Author	*Gregg Jorgen Suaning (Univ. of New South Wales, Australia)
Page	pp. 291 - 294
Detailed information (abstract, keywords, etc)
Slides

4S-3 (Time: 11:15 - 11:45)

Title	(Invited Paper) Design Considerations and Clinical Applications of Closed-Loop Neural Disorder Control SoCs
Author	*Chung-Yu Wu, Cheng-Hsiang Cheng, Yi-Huan Ou-Yang (National Chiao Tung Univ., Taiwan), Chiung-Chu Chen (Chang Gung Memorial Hospital and Univ., Taiwan), Wei-Ming Chen, Ming-Dou Ker, Chen-Yi Lee (National Chiao Tung Univ., Taiwan), Sheng-Fu Liang, Fu-Zen Shaw (National Cheng Kung Univ., Taiwan)
Page	pp. 295 - 298
Detailed information (abstract, keywords, etc)
Slides

4S-4 (Time: 11:45 - 12:15)

Title	(Panel Discussion) Emerging Technologies for Biomedical Applications: Artificial Vision Systems and Brain Machine Interface
Author	*Panelists: Jun Ohta (NAIST, Japan), Gregg Jorgen Suaning (Univ. of New South Wales, Australia), Chung-Yu Wu (National Chiao Tung Univ., Taiwan), Napoleon Torres-Martinez (CEA-Leti, France)
Page	p. 299
Detailed information (abstract, keywords, etc)
Slides

Session 4A Power and Thermal Management
Time: 10:15 - 12:20 Wednesday, January 18, 2017
Location: Room 102
Chair: Koji Inoue (Kyushu Univ., Japan)

4A-1 (Time: 10:15 - 10:40)

Title	A Tool for Synthesizing Power-Efficient and Custom-Tailored Wavelength-Routed Optical Rings
Author	*Marta Ortín-Obón (Univ. of Zaragoza, Spain), Luca Ramini (Univ. of Ferrara, Italy), Víctor Viñals-Yúfera (Univ. of Zaragoza, Spain), Davide Bertozzi (Univ. of Ferrara, Italy)
Page	pp. 300 - 305
Detailed information (abstract, keywords, etc)
Slides

4A-2 (Time: 10:40 - 11:05)

Title	Islands of Heaters: A Novel Thermal Management Framework for Photonic NoCs
Author	*Dharanidhar Dang (Texas A&M Univ., U.S.A.), Sai Vineel Reddy Chittamuru (Colorado State Univ., U.S.A.), Rabi N Mahapatra (Texas A&M Univ., U.S.A.), Sudeep Pasricha (Colorado State Univ., U.S.A.)
Page	pp. 306 - 311
Detailed information (abstract, keywords, etc)
Slides

4A-3 (Time: 11:05 - 11:30)

Title	Energy-Aware Loops Mapping on Multi-Vdd CGRAs without Performance Degradation
Author	*Jiangyuan Gu, Shouyi Yin, Leibo Liu, Shaojun Wei (Tsinghua Univ., China)
Page	pp. 312 - 317
Detailed information (abstract, keywords, etc)
Slides

4A-4 (Time: 11:30 - 11:55)

Title	Algorithm Accelerations for Luminescent Solar Concentrator-Enhanced Reconfigurable Onboard Photovoltaic System
Author	*Caiwen Ding (Syracuse Univ., U.S.A.), Ji Li (Univ. of Southern California, U.S.A.), Weiwei Zheng (Syracuse Univ., U.S.A.), Naehyuck Chang (Korea Advanced Institute of Science and Engineering (KAIST), Republic of Korea), Xue Lin (Northeastern Univ., U.S.A.), Yanzhi Wang (Syracuse Univ., U.S.A.)
Page	pp. 318 - 323
Detailed information (abstract, keywords, etc)
Slides

4A-5 (Time: 11:55 - 12:20)

Title	Two-stage Thermal-Aware Scheduling of Task Graphs on 3D Multi-cores Exploiting Application and Architecture Characteristics
Author	*Zuomin Zhu (Hong Kong Univ. of Science and Tech., Hong Kong), Vivek Chaturvedi (Nanyang Technological Univ., Singapore), Amit Kumar Singh (Univ. of Southampton, U.K.), Wei Zhang (Hong Kong Univ. of Science and Tech., Hong Kong), Yingnan Cui (Nanyang Technological Univ., Singapore)
Page	pp. 324 - 329
Detailed information (abstract, keywords, etc)
Slides

Session 4B Emerging Topics in Hardware Security
Time: 10:15 - 12:20 Wednesday, January 18, 2017
Location: Room 104
Chairs: Xiaoxiao Wang (Beihang Univ., China), Kazuo Sakiyama (Univ. of Electrical Communications, Japan)

4B-1 (Time: 10:15 - 10:40)

Title	Ensuring System Security through Proximity Based Authentication
Author	Joshua Marxen, *Alex Orailoglu (Univ. of California, San Diego, U.S.A.)
Page	pp. 330 - 335
Detailed information (abstract, keywords, etc)

4B-2 (Time: 10:40 - 11:05)

Title	VOLtA: Voltage Over-scaling Based Lightweight Authentication for IoT Applications
Author	Md Tanvir Arafin, Mingze Gao, *Gang Qu (Univ. of Maryland, College Park, U.S.A.)
Page	pp. 336 - 341
Detailed information (abstract, keywords, etc)
Slides

4B-3 (Time: 11:05 - 11:30)

Title	Security Analysis of Anti-SAT
Author	Muhammad Yasin (New York Univ., U.S.A.), Bodhisatwa Mazumdar, *Ozgur Sinanoglu (New York Univ. Abu Dhabi, United Arab Emirates), Jeyavijayan Rajendran (Univ. of Texas, Dallas, U.S.A.)
Page	pp. 342 - 347
Detailed information (abstract, keywords, etc)

4B-4 (Time: 11:30 - 11:55)

Title	Exploiting Accelerated Aging Effect for On-line Configurability and Hardware Tracking
Author	Yang You, *Jie Gu (Northwestern Univ., U.S.A.)
Page	pp. 348 - 353
Detailed information (abstract, keywords, etc)
Slides

4B-5 (Time: 11:55 - 12:20)

Title	SGXCrypter: IP Protection for Portable Executables Using Intel's SGX Technology
Author	*Dimitrios Tychalas (New York Univ. Abu Dhabi, United Arab Emirates), Nektarios Georgios Tsoutsos (New York Univ. Polytechnic School of Engineering, U.S.A.), Michail Maniatakos (New York Univ. Abu Dhabi, United Arab Emirates)
Page	pp. 354 - 359
Detailed information (abstract, keywords, etc)
Slides

Session 4C Manufacturability and Emerging Techniques
Time: 10:15 - 12:20 Wednesday, January 18, 2017
Location: Room 105
Chairs: Taewhan Kim (Seoul National Univ., Republic of Korea), Wenjing Rao (Univ. of Illinois, U.S.A.)

4C-1 (Time: 10:15 - 10:40)

Title	Network Flow Based Cut Redistribution and Insertion for Advanced 1D Layout Design
Author	*Ye Zhang, Wai-Shing Luk, Fan Yang, Changhao Yan (Fudan Univ., China), Hai Zhou (Northwestern Univ., U.S.A.), Dian Zhou (Univ. of Texas, Dallas, U.S.A.), Xuan Zeng (Fudan Univ., China)
Page	pp. 360 - 365
Detailed information (abstract, keywords, etc)
Slides

4C-2 (Time: 10:40 - 11:05)

Title	An Efficient Algorithm for Stencil Planning and Optimization in E-Beam Lithography
Author	*Jiabei Ge, Changhao Yan (Fudan Univ., China), Hai Zhou (Northwestern Univ., U.S.A.), Dian Zhou (Univ. of Texas, Dallas, U.S.A.), Xuan Zeng (Fudan Univ., China)
Page	pp. 366 - 371
Detailed information (abstract, keywords, etc)
Slides

4C-3 (Time: 11:05 - 11:30)

Title	Flexible Interconnect in 2.5D ICs to Minimize the Interposer's Metal Layers
Author	Daniel P. Seemuth, *Azadeh Davoodi, Katherine Morrow (Univ. of Wisconsin - Madison, U.S.A.)
Page	pp. 372 - 377
Detailed information (abstract, keywords, etc)
Slides

4C-4 (Time: 11:30 - 11:55)

Title	Optimizing DSA-MP Decomposition and Redundant Via Insertion with Dummy Vias
Author	Chung-Yao Hung, *Peng-Yi Chou, Wai-Kei Mak (National Tsing Hua Univ., Taiwan)
Page	pp. 378 - 383
Detailed information (abstract, keywords, etc)
Slides

4C-5 (Time: 11:55 - 12:20)

Title	Design of Multiple Fanout Clock Distribution Network for Rapid Single Flux Quantum Technology
Author	Naveen Katam, Alireza Shafaei, *Massoud Pedram (Univ. of Southern California, U.S.A.)
Page	pp. 384 - 389
Detailed information (abstract, keywords, etc)
Slides

Session 5S (Designers' Forum) Advanced Devices and Networks for IoT Applications
Time: 13:50 - 15:30 Wednesday, January 18, 2017
Location: Room 103
Organizers: Koichiro Yamashita (Fujitsu Labs., Japan), Tatsuo Shiozawa (Toshiba, Japan), Masaru Kokubo (Hitachi, Japan), Chair: Koichiro Yamashita (Fujitsu Labs., Japan)

5S-1 (Time: 13:50 - 14:15)

Title	(Invited Paper) Implementation of Reliable and Maintenance-Free Wireless Multihop Networks
Author	Ren Sakata, Suhwuk Kim, Hiroki Kudo (Toshiba, Japan)
Detailed information (abstract, keywords, etc)

5S-2 (Time: 14:15 - 14:40)

Title	(Invited Paper) High-performance and Low-power Embedded Memory for Edge Computing System
Author	Masami Nakajima (Renesas Electronics, Japan)
Detailed information (abstract, keywords, etc)

5S-3 (Time: 14:40 - 15:05)

Title	(Invited Paper) Ultra-Low-Power Wireless Sensor Nodes with Energy Harvesting, and IoT gateway Technology
Author	Hiroki Morimura (NTT, Japan)
Detailed information (abstract, keywords, etc)

5S-4 (Time: 15:05 - 15:30)

Title	(Invited Paper) Fast Channel Switching Technique for Interference Avoidance with 5 GHz Dual Channel Wireless LAN
Author	Takashi Takeuchi (Hitachi, Japan)
Detailed information (abstract, keywords, etc)

Session 5A Approximate Computation for Energy Efficiency
Time: 13:50 - 15:30 Wednesday, January 18, 2017
Location: Room 102
Chairs: Li Shang (Univ. of Colorado, U.S.A.), Shinobu Miwa (Univ. of Electro-Communications, Japan)

5A-1 (Time: 13:50 - 14:15)

Title	A Novel Data Format for Approximate Arithmetic Computing
Author	*Mingze Gao, Qian Wang, Akshaya Sharma Kankanhalli Nagendra, Gang Qu (Univ. of Maryland, College Park, U.S.A.)
Page	pp. 390 - 395
Detailed information (abstract, keywords, etc)
Slides

5A-2 (Time: 14:15 - 14:40)

Title	ApproxPIM: Exploiting Realistic 3D-stacked DRAM for Energy-Efficient Processing In-memory
Author	*Yibin Tang, Ying Wang, Huawei Li, Xiaowei Li (Chinese Academy of Sciences, China)
Page	pp. 396 - 401
Detailed information (abstract, keywords, etc)
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5A-3 (Time: 14:40 - 15:05)

Title	ApproxEye: Enabling Approximate Computation Reuse for Microrobotic computer Vision
Author	Xin He (Chinese Academy of Sciences/Univ. of Chinese Academy of Sciences, China), *Guihai Yan (Chinese Academy of Sciences, China), Faqiang Sun (Chinese Academy of Sciences/Univ. of Chinese Academy of Sciences, China), Yinhe Han, Xiaowei Li (Chinese Academy of Sciences, China)
Page	pp. 402 - 407
Detailed information (abstract, keywords, etc)
Slides

5A-4 (Time: 15:05 - 15:30)

Title	On Resilient Task Allocation and Scheduling with Uncertain Quality Checkers
Author	*Qian Zhang, Ting Wang, Qiang Xu (Chinese Univ. of Hong Kong, Hong Kong)
Page	pp. 408 - 413
Detailed information (abstract, keywords, etc)
Slides

Session 5B Advance Test and Fault Tolerant Technologies
Time: 13:50 - 15:30 Wednesday, January 18, 2017
Location: Room 104
Chairs: Satoshi Ohtake (Oita Univ., Japan), Ying Wang (Chinese Academy of Sciences, China)

5B-1 (Time: 13:50 - 14:15)

Title	An Artificial Neural Network Approach for Screening Test Escapes
Author	Fan Lin (Univ. of California, Santa Barbara, U.S.A.), *Kwang-Ting Tim Cheng (Hong Kong Univ. of Science and Tech., Hong Kong)
Page	pp. 414 - 419
Detailed information (abstract, keywords, etc)
Slides

5B-2 (Time: 14:15 - 14:40)

Title	Processor Shield for L1 Data Cache Software-Based On-line Self-testing
Author	*Ching-Wen Lin, Chung-Ho Chen (National Cheng Kung Univ., Taiwan)
Page	pp. 420 - 425
Detailed information (abstract, keywords, etc)
Slides

5B-3 (Time: 14:40 - 15:05)

Title	Predicting Vt Variation and Static IR Drop of Ring Oscillators Using Model-Fitting Techniques
Author	Tzu-Hsuan Huang, *Wei-Tse Hung, Hao-Yu Yang, Wen-Hsiang Chang (National Chiao Tung Univ., Taiwan), Ying-Yen Chen, Chun-Yi Kuo, Jih-Nung Lee (Realtek Semiconductor, Taiwan), Mango Chia-Tso Chao (National Chiao Tung Univ., Taiwan)
Page	pp. 426 - 431
Detailed information (abstract, keywords, etc)
Slides

5B-4 (Time: 15:05 - 15:30)

Title	A Local Reconfiguration Based Scalable Fault Tolerant Many-processor Array
Author	Soumya Banerjee, *Wenjing Rao (Univ. of Illinois, Chicago, U.S.A.)
Page	pp. 432 - 437
Detailed information (abstract, keywords, etc)

Session 5C Advanced Placement and Routing Techniques
Time: 13:50 - 15:30 Wednesday, January 18, 2017
Location: Room 105
Chairs: Seokhyeong Kang (UNIST, Republic of Korea), Wai-Kei Mak (National Tsing Hua Univ., Taiwan)

5C-1 (Time: 13:50 - 14:15)

Title	Regularity-aware Routability-driven Placement Prototyping Algorithm for Hierarchical Mixed-size Circuits
Author	Jai-Ming Lin, Bo-Heng Yu, *Li-Yen Chang (National Cheng Kung Univ., Taiwan)
Page	pp. 438 - 443
Detailed information (abstract, keywords, etc)
Slides

5C-2 (Time: 14:15 - 14:40)

Title	Floorplan and Placement Methodology for Improved Energy Reduction in Stacked Power-Domain Design
Author	*Kristof Blutman, Hamed Fatemi (NXP Semiconductors, Netherlands), Andrew B. Kahng (Univ. of California, San Diego, U.S.A.), Ajay Kapoor (NXP Semiconductors, Netherlands), Jiajia Li (Univ. of California, San Diego, U.S.A.), José Pineda de Gyvez (NXP Semiconductors, U.S.A.)
Page	pp. 444 - 449
Detailed information (abstract, keywords, etc)

5C-3 (Time: 14:40 - 15:05)

Title	An Effective Legalization Algorithm for Mixed-Cell-Height Standard Cells
Author	*Chao-Hung Wang, Yen-Yi Wu (National Taiwan Univ., Taiwan), Jianli Chen (Fuzhou Univ., China), Yao-Wen Chang, Sy-Yen Kuo (National Taiwan Univ., Taiwan), Wenxing Zhu, Genghua Fan (Fuzhou Univ., China)
Page	pp. 450 - 455
Detailed information (abstract, keywords, etc)
Slides

5C-4 (Time: 15:05 - 15:30)

Title	Delay-driven Layer Assignment for Advanced Technology Nodes
Author	Szu-Yuan Han (National Tsing Hua Univ., Taiwan), Wen-Hao Liu (Cadence Design Systems, U.S.A.), Rickard Ewetz (Univ. of Central Florida, U.S.A.), Cheng-Kok Koh (Purdue Univ., U.S.A.), Kai-Yuan Chao (Intel, U.S.A.), *Ting-Chi Wang (National Tsing Hua Univ., Taiwan)
Page	pp. 456 - 462
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Slides

Session 6S (Designers' Forum) Panel Discussion: What is future AI we will create ? - "Doraemon" or "Terminator" ? -
Time: 15:50 - 17:30 Wednesday, January 18, 2017
Location: Room 103
Organizers: Hiroe Iwasaki (NTT, Japan), Sunao Torii (ExaScaler, Japan), Akihiko Inoue (Panasonic, Japan), Chair: Satoshi Kurihara (Univ. of Electro-Communications, Japan)

6S-1 (Time: 15:50 - 17:30)

Title	(Panel Discussion) What is future AI we will create? - "Doraemon" or "Terminator" ? -
Author	Panelists: Hiroshi Yamakawa (dwango, Japan), Luca Rigazio (Panasonic Silicon Valley Lab, Japan), Takeshi Yamada (NTT, Japan), Akira Naruse (NVIDIA, Japan), Shinji Nakadai (NEC, Japan)
Detailed information (abstract, keywords, etc)

Session 6A Recent Advances in Circuit Simulation and Optimization
Time: 15:50 - 17:30 Wednesday, January 18, 2017
Location: Room 102
Chairs: Markus Olbrich (Univ. of Hannover, Germany), Ibrahim (Abe) Elfadel (Masdar Inst. of Science and Tech., United Arab Emirates)

6A-1 (Time: 15:50 - 16:15)

Title	STEAM: Spline-based Tables for Efficient and Accurate Device Modelling
Author	*Archit Gupta, Tianshi Wang, Ahmet Gokcen Mahmutoglu, Jaijeet Roychowdhury (UC Berkeley, U.S.A.)
Page	pp. 463 - 468
Detailed information (abstract, keywords, etc)
Slides

6A-2 (Time: 16:15 - 16:40)

Title	A Time Domain Behavioral Model for Oscillators Considering Flicker Noise
Author	*Hui Zhang, Bo Wang (Peking Univ. Shenzhen Graduate School, China)
Page	pp. 469 - 474
Detailed information (abstract, keywords, etc)
Slides

6A-3 (Time: 16:40 - 17:05)

Title	Parasitic-Aware GP-based Many-objective Sizing Methodology for Analog and RF Integrated Circuits
Author	*Tuotian Liao, Lihong Zhang (Memorial Univ. of Newfoundland, Canada)
Page	pp. 475 - 480
Detailed information (abstract, keywords, etc)
Slides

6A-4 (Time: 17:05 - 17:30)

Title	High-Speed Stochastic Circuits Using Synchronous Analog Pulses
Author	*M. Hassan Najafi, David J. Lilja (Univ. of Minnesota, twin cities, U.S.A.)
Page	pp. 481 - 487
Detailed information (abstract, keywords, etc)
Slides

Session 6B Application-Aware Embedded Architecture Design
Time: 15:50 - 17:30 Wednesday, January 18, 2017
Location: Room 104
Chairs: Chun-Yi Lee (NTHU, Taiwan), Shao-Yun Fang (National Taiwan Univ. of Science and Tech., Taiwan)

6B-1 (Time: 15:50 - 16:15)

Title	Throughput Optimization for Streaming Applications on CPU-FPGA Heterogeneous Systems
Author	*Xuechao Wei, Yun Liang (Peking Univ., China), Tao Wang (Peking Univ./PKU-UCLA Joint Research Institute in Science and Engineering, China), Songwu Lu, Jason Cong (Peking Univ./UCLA/PKU-UCLA Joint Research Institute in Science and Engineering, U.S.A.)
Page	pp. 488 - 493
Detailed information (abstract, keywords, etc)
Slides

6B-2 (Time: 16:15 - 16:40)

Title	Dark Silicon-Aware Hardware-Software Collaborated Design for Heterogeneous Many-Core Systems
Author	Lei Yang, *Weichen Liu (Chongqing Univ., China), Nan Guan (Hong Kong Polytechnic Univ., Hong Kong), Mengquan Li, Peng Chen, Edwin H. M. Sha (Chongqing Univ., China)
Page	pp. 494 - 499
Detailed information (abstract, keywords, etc)

6B-3 (Time: 16:40 - 17:05)

Title	Non-Intrusive Dynamic Profiler for Multicore Embedded Systems
Author	Sudarshan Sargur, *Roman Lysecky (Univ. of Arizona, U.S.A.)
Page	pp. 500 - 505
Detailed information (abstract, keywords, etc)
Slides

6B-4 (Time: 17:05 - 17:30)

Title	Design of A Pre-Scheduled Data Bus for Advanced Encryption Standard Encrypted System-on-Chips
Author	Xiaokun Yang (Univ. of Houston Clear Lake, U.S.A.), *Wujie Wen (Florida International Univ., U.S.A.)
Page	pp. 506 - 511
Detailed information (abstract, keywords, etc)
Slides

Session 6C Advances in Microfluidic Biochips
Time: 15:50 - 17:30 Wednesday, January 18, 2017
Location: Room 105
Chairs: Tohru Ishihara (Kyoto Univ., Japan), Weikang Qian (Shanghai Jiao Tong Univ., China)

6C-1 (Time: 15:50 - 16:15)

Title	Piracy Prevention of Digital Microfluidic Biochips
Author	*Ching-Wei Hsieh (National Tsing Hua Univ., Taiwan), Zipeng Li (Duke Univ., U.S.A.), Tsung-Yi Ho (National Tsing Hua Univ., Taiwan)
Page	pp. 512 - 517
Detailed information (abstract, keywords, etc)
Slides

6C-2 (Time: 16:15 - 16:40)

Title	On Reliability Hardening in Cyber-Physical Digital-Microfluidic Biochips
Author	*Guan-Ruei Lu, Guan-Ming Huang (National Chiao Tung Univ., Taiwan), Ansuman Banerjee, Bhargab B. Bhattacharya (Advanced Computing & Microelectronics Unit, Indian Statistical Institute, India), Tsung-Yi Ho (National Tsing Hua Univ., Taiwan), Hung-Ming Chen (National Chiao Tung Univ., Taiwan)
Page	pp. 518 - 523
Detailed information (abstract, keywords, etc)
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6C-3 (Time: 16:40 - 17:05)

Title	Hamming-Distance-Based Valve-Switching Optimization for Control-Layer Multiplexing in Flow-Based Microfluidic Biochips
Author	*Qin Wang, Shiliang Zuo, Hailong Yao (Tsinghua Univ., China), Tsung-Yi Ho (National Tsing Hua Univ., Taiwan), Bing Li, Ulf Schlichtmann (Tech. Univ. of Munich, Germany), Yici Cai (Tsinghua Univ., China)
Page	pp. 524 - 529
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Slides

6C-4 (Time: 17:05 - 17:30)

Title	Close-to-Optimal Placement and Routing for Continuous-Flow Microfluidic Biochips
Author	*Andreas Grimmer (Johannes Kepler Univ., Austria), Qin Wang, Hailong Yao (Tsinghua Univ., China), Tsung-Yi Ho (National Tsing Hua Univ., Taiwan), Robert Wille (Johannes Kepler Univ., Austria)
Page	pp. 530 - 535
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Thursday, January 19, 2017

Session 3K Keynote III
Time: 9:00 - 9:50 Thursday, January 19, 2017
Location: International Conference Room
Chair: Kazutoshi Kobayashi (Kyoto Inst. of Tech., Japan)

3K-1 (Time: 9:00 - 9:50)

Title	(Keynote Address) All-Programmable FPGAs: More Powerful Devices Require More Powerful Tools
Author	Steve Trimberger (Xilinx Research Labs, U.S.A.)
Page	p. 536
Detailed information (abstract, keywords, etc)

Session 7S (Special Session) When Backend Meets Frontend: Cross-Layer Design & Optimization for System Robustness
Time: 10:15 - 12:15 Thursday, January 19, 2017
Location: Room 103
Organizers/Chairs: Cheng Zhuo (Zhejiang Univ.), Masanori Hashimoto (Osaka Univ., Japan)

7S-1 (Time: 10:15 - 10:45)

Title	(Invited Paper) Containing Guardbands
Author	*Hussam Amrouch, Jörg Henkel (Karlsruhe Inst. of Tech., Germany)
Page	pp. 537 - 542
Detailed information (abstract, keywords, etc)

7S-2 (Time: 10:45 - 11:15)

Title	(Invited Paper) Pattern Based Runtime Voltage Emergency Prediction: An Instruction-Aware Block Sparse Compressed Sensing Approach
Author	Yu-Guang Chen (National Tsing Hua Univ., Taiwan), Michihiro Shintani, *Takashi Sato (Kyoto Univ., Japan), Yiyu Shi (Univ. of Notre Dame, U.S.A.), Shih-Chieh Chang (National Tsing Hua Univ., Taiwan)
Page	pp. 543 - 548
Detailed information (abstract, keywords, etc)

7S-3 (Time: 11:15 - 11:45)

Title	(Invited Paper) Heterogeneous Chip Power Delivery Modeling and Co-Synthesis for Practical 3DIC Realization
Author	Wei-Hsun Liao (National Chiao Tung Univ., Taiwan), Chang-Tzu Lin (ITRI, Taiwan), Sheng-Hsin Fang, Chien-Chia Huang, *Hung-Ming Chen (National Chiao Tung Univ., Taiwan), Ding-Ming Kwai, Yung-Fa Chou (ITRI, Taiwan)
Page	pp. 549 - 553
Detailed information (abstract, keywords, etc)

7S-4 (Time: 11:45 - 12:15)

Title	(Invited Paper) CN-SIM: A Cycle-Accurate Full System Power Delivery Noise Simulator
Author	*Kassan Unda (Univ. of Notre Dame, U.S.A.), Chung-Han Chou, Shih-Chieh Chang (National Tsing Hua Univ., Taiwan), Cheng Zhuo (Zhejiang Univ., China), Yiyu Shi (Univ. of Notre Dame, U.S.A.)
Page	pp. 554 - 559
Detailed information (abstract, keywords, etc)

Session 7A NVM/Flash: From Advanced Storage Design to Emerging Applications
Time: 10:15 - 12:20 Thursday, January 19, 2017
Location: Room 102
Chairs: Sungjoo Yoo (Seoul National Univ., Republic of Korea), Ya-Shu Chen (National Taiwan Univ. of Science and Tech., Taiwan)

7A-1 (Time: 10:15 - 10:40)

Title	Improving LDPC Performance Via Asymmetric Sensing Level Placement on Flash Memory
Author	*Qiao Li, Liang Shi (Chongqing Univ., China), Chun Jason Xue (City Univ. of Hong Kong, Hong Kong), Qingfeng Zhuge, Edwin H.-M. Sha (Chongqing Univ., China)
Page	pp. 560 - 565
Detailed information (abstract, keywords, etc)
Slides

7A-2 (Time: 10:40 - 11:05)

Title	A Flash Scheduling Strategy for Current Capping in Multi-Power-Mode SSDs
Author	Li-Pin Chang, Chia-Hsiang Cheng, *Kai-Hsiang Lin (National Chiao Tung Univ., Taiwan)
Page	pp. 566 - 571
Detailed information (abstract, keywords, etc)
Slides

7A-3 (Time: 11:05 - 11:30)

Title	Temperature-Aware Data Allocation Strategy for 3D Charge-Trap Flash Memory
Author	*Yi Wang, Mingxu Zhang (Shenzhen Univ., China), Jing Yang (Harbin Inst. of Tech., China)
Page	pp. 572 - 577
Detailed information (abstract, keywords, etc)
Slides

7A-4 (Time: 11:30 - 11:55)

Title	Scalable Frequent-Pattern Mining on Nonvolatile Memories
Author	*Yi Lin (Chongqing Univ., China), Po-Chun Huang (Yuan Ze Univ., Taiwan), Duo Liu, Liang Liang (Chongqing Univ., China)
Page	pp. 578 - 583
Detailed information (abstract, keywords, etc)
Slides

7A-5 (Time: 11:55 - 12:20)

Title	KVFTL: Optimization of Storage Space Utilization for Key-Value-Specific Flash Storage Devices
Author	*Yen-Ting Chen (National Tsing Hua Univ., Taiwan), Ming-Chang Yang, Yuan-Hao Chang, Tseng-Yi Chen (Academia Sinica, Taiwan), Hsin-Wen Wei (Tamkang Univ., Taiwan), Wei-Kuan Shih (National Tsing Hua Univ., Taiwan)
Page	pp. 584 - 590
Detailed information (abstract, keywords, etc)
Slides

Session 7B Hardware Diversity and Hardware Trojan
Time: 10:15 - 12:20 Thursday, January 19, 2017
Location: Room 104
Chairs: Wujie Wen (Florida International Univ., U.S.A.), Chip Hong Chang (Nanyang Technological Univ., Singapore)

7B-1 (Time: 10:15 - 10:40)

Title	Trojan Localization Using Symbolic Algebra
Author	Farimah Farahmandi, Yuanwen Huang, *Prabhat Mishra (Univ. of Florida, U.S.A.)
Page	pp. 591 - 597
Detailed information (abstract, keywords, etc)
Slides

7B-2 (Time: 10:40 - 11:05)

Title	Detecting Hardware Trojans in Unspecified Functionality Through Solving Satisfiability Problems
Author	*Nicole Fern (UC Santa Barbara, U.S.A.), Ismail San (Anadolu Univ., Turkey), Kwang-Ting (Tim) Cheng (Hong Kong Univ. of Science and Tech., Hong Kong)
Page	pp. 598 - 604
Detailed information (abstract, keywords, etc)
Slides

7B-3 (Time: 11:05 - 11:30)

Title	Routing Perturbation for Enhanced Security in Split Manufacturing
Author	*Yujie Wang, Pu Chen, Jiang Hu (Texas A&M Univ., U.S.A.), Jeyavijayan Rajendran (Univ. of Texas, Dallas, U.S.A.)
Page	pp. 605 - 610
Detailed information (abstract, keywords, etc)
Slides

7B-4 (Time: 11:30 - 11:55)

Title	MUTARCH: Architectural Diversity for FPGA Device and IP Security
Author	*Robert Karam, Tamzidul Hoque (Univ. of Florida, U.S.A.), Sandip Ray (NXP Semiconductors, U.S.A.), Mark Tehranipoor, Swarup Bhunia (Univ. of Florida, U.S.A.)
Page	pp. 611 - 616
Detailed information (abstract, keywords, etc)
Slides

7B-5 (Time: 11:55 - 12:20)

Title	Security Vulnerability Analysis of Design-for-Test Exploits for Asset Protection in SoCs
Author	Gustavo K. Contreras, Adib Nahiyan, Swarup Bhunia, Domenic Forte, *Mark Tehranipoor (Univ. of Florida, U.S.A.)
Page	pp. 617 - 622
Detailed information (abstract, keywords, etc)

Session 7C Hardware Accelerator for Emerging Applications
Time: 10:15 - 12:20 Thursday, January 19, 2017
Location: Room 105
Chairs: Tohru Ishihara (Kyoto Univ., Japan), Yongpan Liu (Tsinghua Univ., China)

7C-1 (Time: 10:15 - 10:40)

Title	Towards Scalable and Efficient GPU-Enabled Slicing Acceleration in Continuous 3D Printing
Author	Aosen Wang, Chi Zhou (State Univ. of New York, Buffalo, U.S.A.), *Zhanpeng Jin (State Univ. of New York, Binghamton, U.S.A.), Wenyao Xu (State Univ. of New York, Buffalo, U.S.A.)
Page	pp. 623 - 628
Detailed information (abstract, keywords, etc)
Slides

7C-2 (Time: 10:40 - 11:05)

Title	FPGA-based Accelerator for Long Short-Term Memory Recurrent Neural Networks
Author	*Yijin Guan, Zhihang Yuan (Peking Univ., China), Guangyu Sun (Peking Univ./PKU-UCLA Joint Research Institute in Science and Engineering, China), Jason Cong (Peking Univ./PKU-UCLA Joint Research Institute in Science and Engineering/Univ. of California, Los Angeles, U.S.A.)
Page	pp. 629 - 634
Detailed information (abstract, keywords, etc)
Slides

7C-3 (Time: 11:05 - 11:30)

Title	Fine-Grained Accelerators for Sparse Machine Learning Workloads
Author	Asit K. Mishra, *Eriko Nurvitadhi, Ganesh Venkatesh, Jonathan Pearce, Debbie Marr (Intel, U.S.A.)
Page	pp. 635 - 640
Detailed information (abstract, keywords, etc)
Slides

7C-4 (Time: 11:30 - 11:55)

Title	High Throughput Hardware Architecture for Accurate Semi-Global Matching
Author	Yan Li, Chen Yang, Wei Zhong, Zhiwei Li, *Song Chen (Univ. of Science and Tech. of China, China)
Page	pp. 641 - 646
Detailed information (abstract, keywords, etc)
Slides

7C-5 (Time: 11:55 - 12:20)

Title	A Memristor-based Neuromorphic Engine with a Current Sensing Scheme for Artificial Neural Network Applications
Author	Chenchen Liu, Qing Yang (Univ. of Pittsburgh, U.S.A.), Chi Zhang, Hao Jiang (San Francisco State Univ., U.S.A.), Qing Wu (Air Force Research Lab, U.S.A.), *Hai (Helen) Li (Univ. of Pittsburgh, U.S.A.)
Page	pp. 647 - 652
Detailed information (abstract, keywords, etc)

Session 8S (Designers' Forum) Advanced Automotive Security
Time: 13:50 - 15:30 Thursday, January 19, 2017
Location: Room 103
Organizers: Shinichi Shibahara (Renesas System Design, Japan), Akihiko Inoue (Panasonic, Japan), Chair: Shinichi Shibahara (Renesas System Design, Japan)

8S-1 (Time: 13:50 - 14:15)

Title	(Invited Paper) Using Security Applications for Automotive Hardware Security Modules
Author	Dennis Kengo Oka (ETAS, Japan)
Detailed information (abstract, keywords, etc)

8S-2 (Time: 14:15 - 14:40)

Title	(Invited Paper) An Embedded Hardware Security Module for Automotive ECUs
Author	Yasuhisa Shimazaki (Renesas Electronics, Japan)
Detailed information (abstract, keywords, etc)

8S-3 (Time: 14:40 - 15:05)

Title	(Invited Paper) Security Hardware for Automotive Applications
Author	Takeshi Fujino (Ritsumeikan Univ., Japan)
Detailed information (abstract, keywords, etc)

8S-4 (Time: 15:05 - 15:30)

Title	(Invited Paper) Physical and Logical Attacks against LSI Chips and Their Countermeasures
Author	Shinichi Kawamura (Toshiba, Japan)
Detailed information (abstract, keywords, etc)

Session 8A Scheduling, Resource Management, and Simulation for Multi-Core Systems
Time: 13:50 - 15:30 Thursday, January 19, 2017
Location: Room 102
Chairs: Yuko Hara-Azumi (Tokyo Inst. of Tech., Japan), Yi Wang (Shenzhen Univ., China)

8A-1 (Time: 13:50 - 14:15)

Title	An Adaptive On-line CPU-GPU Governor for Games on Mobile Devices
Author	Po-Kai Chuang, *Ya-Shu Chen, Po-Hao Huang (National Taiwan Univ. of Science and Tech., Taiwan)
Page	pp. 653 - 658
Detailed information (abstract, keywords, etc)
Slides

8A-2 (Time: 14:15 - 14:40)

Title	A Static Scheduling Approach to Enable Safety-Critical OpenMP Applications
Author	Alessandra Melani (Scuola Superiore Sant'Anna, Italy), *Maria A. Serrano (Barcelona Supercomputing Center and Technical Univ. of Catalonia, Spain), Marko Bertogna (Univ. di Modena e Reggio Emilia, Italy), Isabella Cerutti (Scuola Superiore Sant'Anna, Italy), Eduardo Quiñones (Barcelona Supercomputing Center, Spain), Giorgio Buttazzo (Scuola Superiore Sant'Anna, Italy)
Page	pp. 659 - 665
Detailed information (abstract, keywords, etc)
Slides

8A-3 (Time: 14:40 - 15:05)

Title	Communication Driven Remapping of Processing Element (PE) in Fault-tolerant NoC-based MPSoCs
Author	Chia-Ling Chen, *Yen-Hao Chen, TingTing Hwang (National Tsing Hua Univ., Taiwan)
Page	pp. 666 - 671
Detailed information (abstract, keywords, etc)
Slides

8A-4 (Time: 15:05 - 15:30)

Title	Detailed and Highly Parallelizable Cycle-Accurate Network-on-Chip Simulation on GPGPU
Author	*Amir Charif, Alexandre Coelho, Nacer-Eddine Zergainoh, Michael Nicolaidis (TIMA Lab., France)
Page	pp. 672 - 677
Detailed information (abstract, keywords, etc)
Slides

Session 8B Machine Learning: Acceleration and Application
Time: 13:50 - 15:30 Thursday, January 19, 2017
Location: Room 104
Chairs: Weichen Liu (Chongqing Univ., China), Nan Guan (Hong Kong Polytechnic Univ., Hong Kong)

8B-1 (Time: 13:50 - 14:15)

Title	Spendthrift: Machine Learning Based Resource and Frequency Scaling for Ambient Energy Harvesting Nonvolatile Processors
Author	*Kaisheng Ma, Xueqing Li, Srivatsa Rangachar Srinivasa (Pennsylvania State Univ., U.S.A.), Yongpan Liu (Tsinghua Univ., China), John (Jack) Sampson (Pennsylvania State Univ., U.S.A.), Yuan Xie (Univ. of California, Santa Barbara, U.S.A.), Vijaykrishnan Narayanan (Pennsylvania State Univ., U.S.A.)
Page	pp. 678 - 683
Detailed information (abstract, keywords, etc)

8B-2 (Time: 14:15 - 14:40)

Title	Modular Reinforcement Learning for Self-Adaptive Energy Efficiency Optimization in Multicore System
Author	Zhe Wang, *Zhongyuan Tian, Jiang Xu, Rafael Kioji Vivas Maeda, Haoran Li, Peng Yang, Zhehui Wang, Luan H. K. Duong, Zhifei Wang, Xuanqi Chen (Hong Kong Univ. of Science and Tech., Hong Kong)
Page	pp. 684 - 689
Detailed information (abstract, keywords, etc)
Slides

8B-3 (Time: 14:40 - 15:05)

Title	BHNN: a Memory-Efficient Accelerator for Compressing Deep Neural Networks with Blocked Hashing Techniques
Author	Jingyang Zhu (Hong Kong Univ. of Science and Tech., Hong Kong), *Zhiliang Qian (Shanghai Jiao Tong Univ., China), Chi-Ying Tsui (Hong Kong Univ. of Science and Tech., Hong Kong)
Page	pp. 690 - 695
Detailed information (abstract, keywords, etc)
Slides

8B-4 (Time: 15:05 - 15:30)

Title	Scalable Stochastic-Computing Accelerator for Convolutional Neural Networks
Author	*Hyeonuk Sim, Dong Nguyen, Jongeun Lee (UNIST, Republic of Korea), Kiyoung Choi (Seoul National Univ., Republic of Korea)
Page	pp. 696 - 701
Detailed information (abstract, keywords, etc)
Slides

Session 8C Design Automation and Modeling for Emerging Technologies
Time: 13:50 - 15:30 Thursday, January 19, 2017
Location: Room 105
Chair: Yiran Chen (Univ. of Pittsburgh, U.S.A.)

8C-1 (Time: 13:50 - 14:15)

Title	Reservoir and Mixer Constrained Scheduling for Sample Preparation on Digital Microfluidic Biochips
Author	*Varsha Agarwal, Ananya Singla (Indian Inst. of Tech. Roorkee, India), Mahammad Samiuddin (Indian Inst. of Tech. Kharagpur, India), Sudip Roy (Indian Inst. of Tech. Roorkee, India), Tsung-Yi Ho (National Tsing Hua Univ., Taiwan), Indranil Sengupta (Indian Inst. of Tech. Kharagpur, India), Bhargab B. Bhattacharya (Indian Statistical Institute Kolkata, India)
Page	pp. 702 - 707
Detailed information (abstract, keywords, etc)
Slides

8C-2 (Time: 14:15 - 14:40)

Title	Exact Routing for Micro-Electrode-Dot-Array Digital Microfluidic Biochips
Author	*Oliver Keszocze (Univ. of Bremen, Germany), Zipeng Li (Duke Univ., U.S.A.), Andreas Grimmer, Robert Wille (Johannes Kepler Univ., Austria), Krishnendu Chakrabarty (Duke Univ., U.S.A.), Rolf Drechsler (Univ. of Bremen and DFKI GmbH, Germany)
Page	pp. 708 - 713
Detailed information (abstract, keywords, etc)
Slides

8C-3 (Time: 14:40 - 15:05)

Title	Majority Logic Circuits Optimisation by Node Merging
Author	Chun-Che Chung (National Tsing Hua Univ., Taiwan), Yung-Chih Chen (Yuan Ze Univ., Taiwan), Chun-Yao Wang, *Chia-Cheng Wu (National Tsing Hua Univ., Taiwan)
Page	pp. 714 - 719
Detailed information (abstract, keywords, etc)
Slides

8C-4 (Time: 15:05 - 15:30)

Title	A Statistical STT-RAM Retention Model for Fast Memory Subsystem Designs
Author	Zihao Liu, *Wujie Wen (Florida International Univ., U.S.A.), Lei Jiang (Indiana Univ. Bloomington, U.S.A.), Yier Jin (Univ. of Central Florida, U.S.A.), Gang Quan (Florida International Univ., U.S.A.)
Page	pp. 720 - 725
Detailed information (abstract, keywords, etc)
Slides

Session 9S (Designers' Forum) Advanced Image Sensing and Processing
Time: 15:50 - 17:30 Thursday, January 19, 2017
Location: Room 103
Organizers: Yusuke Oike (Sony Semiconductor Solutions, Japan), Masaitsu Nakajima (Socionext, Japan), Yusuke Oike (Sony Semiconductor Solutions, Japan)

9S-1 (Time: 15:50 - 16:15)

Title	(Invited Paper) An APS-H-Size 250Mpixel CMOS Image Sensor Using Column Single-Slope ADCs with Dual-Gain Amplifiers
Author	Hirofumi Totsuka (Canon, Japan)
Detailed information (abstract, keywords, etc)

9S-2 (Time: 16:15 - 16:40)

Title	(Invited Paper) A 1/1.7-inch 20Mpixel Back-Illuminated Stacked CMOS Image Sensor
Author	Chihiro Okada (Sony Semiconductor Solutions, Japan)
Detailed information (abstract, keywords, etc)

9S-3 (Time: 16:40 - 17:05)

Title	(Invited Paper) Emerging Applications Based on High-speed Computational Vision
Author	Yoshihiro Watanabe (Univ. of Tokyo, Japan)
Detailed information (abstract, keywords, etc)

9S-4 (Time: 17:05 - 17:30)

Title	(Invited Paper) Acceleration of Partial Image Matching on FPGA Platforms Using OpenCL
Author	Noboru Yoneoka (Fujitsu Labs., Japan)
Detailed information (abstract, keywords, etc)

Session 9A New Directions in Networks on Chip
Time: 15:50 - 17:30 Thursday, January 19, 2017
Location: Room 102
Chair: Kun-Chih Chen (National Sun Yat-Sen Univ., Taiwan)

9A-1 (Time: 15:50 - 16:15)

Title	DLPS: Dynamic Laser Power Scaling for Optical Network-on-Chip
Author	*Fan Lan (Zhejiang Univ., China), Rui Wu, Chong Zhang (Univ. of Californis, Santa Barbara, U.S.A.), Yun Pan (Zhejiang Univ., China), Kwang-ting Cheng (Univ. of Californis, Santa Barbara, U.S.A.)
Page	pp. 726 - 731
Detailed information (abstract, keywords, etc)
Slides

9A-2 (Time: 16:15 - 16:40)

Title	Adaptive Load Distribution in Mixed-Critical Networks-On-Chip
Author	*Adam Kostrzewa, Sebastian Tobuschat, Leonardo Ecco, Rolf Ernst (TU Braunschweig, Germany)
Page	pp. 732 - 737
Detailed information (abstract, keywords, etc)
Slides

9A-3 (Time: 16:40 - 17:05)

Title	BoDNoC: Providing Bandwidth-on-Demand Interconnection for Multi-Granularity Memory Systems
Author	*Shiqi Lian, Ying Wang, Yinhe Han, Xiaowei Li (Chinese Academy of Sciences, China)
Page	pp. 738 - 743
Detailed information (abstract, keywords, etc)
Slides

9A-4 (Time: 17:05 - 17:30)

Title	Using Segmentation to Improve Schedulability of RRA-based NoCs with Mixed Traffic
Author	Meng Liu, *Matthias Becker, Moris Behnam, Thomas Nolte (Mälardalen Univ., Sweden)
Page	pp. 744 - 750
Detailed information (abstract, keywords, etc)
Slides

Session 9B Memory Architecture: Now and Future
Time: 15:50 - 17:30 Thursday, January 19, 2017
Location: Room 104
Chairs: Hyung Gyu Lee (Daegu Univ., Republic of Korea), Shimpei Sato (Tokyo Inst. of Tech., Japan)

9B-1 (Time: 15:50 - 16:15)

Title	Building Energy-Efficient Multi-Level Cell STT-RAM Caches with Data Compression
Author	Liu Liu, Ping Chi, Shuangchen Li, Yuanqing Cheng, *Yuan Xie (Univ. of California, Santa Barbara, U.S.A.)
Page	pp. 751 - 756
Detailed information (abstract, keywords, etc)

9B-2 (Time: 16:15 - 16:40)

Title	MPIM: Multi-Purpose In-Memory Processing Using Configurable Resistive Memory
Author	Mohsen Imani, *Yeseong Kim, Tajana Rosing (Univ. of California San Diego, U.S.A.)
Page	pp. 757 - 763
Detailed information (abstract, keywords, etc)

9B-3 (Time: 16:40 - 17:05)

Title	Extending the Lifetime of Object-based NAND Flash Device with STT-RAM/DRAM Hybrid Buffer
Author	Chuhan Min, Jie Guo, Hai Li, *Yiran Chen (Univ. of Pittsburgh, U.S.A.)
Page	pp. 764 - 769
Detailed information (abstract, keywords, etc)

9B-4 (Time: 17:05 - 17:30)

Title	Locality-Aware Bank Partitioning for Shared DRAM MPSoCs
Author	*Yangguo Liu, Junlin Lu, Dong Tong, Xu Cheng (Peking Univ., China)
Page	pp. 770 - 775
Detailed information (abstract, keywords, etc)
Slides

Session 9C Intelligent Computing with Memristor Technologies
Time: 15:50 - 17:30 Thursday, January 19, 2017
Location: Room 105
Chair: Yuan-Hao Chang (Academia Sinica, Taiwan)

9C-1 (Time: 15:50 - 16:15)

Title	Classification Accuracy Improvement for Neuromorphic Computing Systems with One-level Precision Synapses
Author	Yandan Wang, Wei Wen, Linghao Song, *Hai Li (Univ. of Pittsburgh, U.S.A.)
Page	pp. 776 - 781
Detailed information (abstract, keywords, etc)

9C-2 (Time: 16:15 - 16:40)

Title	Binary Convolutional Neural Network on RRAM
Author	*Tianqi Tang, Lixue Xia, Boxun Li, Yu Wang, Huazhong Yang (Tsinghua Univ., China)
Page	pp. 782 - 787
Detailed information (abstract, keywords, etc)
Slides

9C-3 (Time: 16:40 - 17:05)

Title	Algorithm-Hardware Co-Optimization of the Memristor-Based Framework for Solving SOCP and Homogeneous QCQP Problems
Author	*Ao Ren (Syracuse Univ., U.S.A.), Sijia Liu (Univ. of Michigan, U.S.A.), Ruizhe Cai (Syracuse Univ., U.S.A.), Wujie Wen (Florida International Univ., U.S.A.), Pramod K. Varshney, Yanzhi Wang (Syracuse Univ., U.S.A.)
Page	pp. 788 - 793
Detailed information (abstract, keywords, etc)
Slides

9C-4 (Time: 17:05 - 17:30)

Title	Computation-Oriented Fault-Tolerance Schemes for RRAM Computing Systems
Author	Wenqin Huangfu, *Lixue Xia, Ming Cheng, Xiling Yin, Tianqi Tang, Boxun Li (Tsinghua Univ., China), Krishnendu Chakrabarty (Duke Univ., U.S.A.), Yuan Xie (Univ. of California, Santa Barbara, U.S.A.), Yu Wang, Huazhong Yang (Tsinghua Univ., China)
Page	pp. 794 - 799
Detailed information (abstract, keywords, etc)
Slides

The 22nd Asia and South Pacific Design Automation Conference Technical Program

Session Schedule

List of papers

The 22nd Asia and South Pacific Design Automation Conference
Technical Program