The 15th Asia and South Pacific Design Automation Conference
Technical Program

Remark: The presenter of each paper is marked with "*".

Technical Program: SIMPLE version DETAILED version with abstract

Author Index: HERE

Session Schedule

Tuesday, January 19, 2010

Room 101A	Room 101B	Room 101C	Room 101D
Op (Room 101) Opening 8:30 - 9:00
1K (Room 101) Keynote Session I 9:00 - 10:00
2K (Room 101) Keynote Session II 10:20 - 11:20
3K (Room 101) Keynote Session III 11:20 - 12:20
1A Embedded Systems Design Techniques 13:30 - 15:10	1B Advanced Model Order Reduction Technique 13:30 - 15:10	1C Logic Synthesis 13:30 - 15:10	1D Special Session: Techniques for Efficient Energy Harvesting and Generation for Portable and Embedded Systems 13:30 - 15:10
2A Memory Management and Compiler Techniques 15:30 - 17:10	2B Power and Signal Integrity 15:30 - 17:10	2C System-level Simulation 15:30 - 17:10	2D Special Session: 3D Integration and Networks on Chips 15:30 - 17:10

Wednesday, January 20, 2010

Room 101A	Room 101B	Room 101C	Room 101D
3A Emerging Memories and 3D ICs 8:30 - 10:10	3B Macromodeling and Verification of Analog Systems 8:30 - 10:10	3C System-level Modelling and Analysis 8:30 - 10:10	3D Special Session: Recent Advancement in Post-silicon Validation 8:30 - 10:10
4A New Techniques for Beyond-die Routing 10:30 - 12:10	4B Analog Layout and Testing 10:30 - 12:10	4C New Techniques in Technology Mapping 10:30 - 12:10	4D University LSI Design Contest 10:30 - 12:10
5A Clock Network Analysis and Optimization 13:30 - 15:10	5B Test Solutions for Emerging Applications 13:30 - 15:10	5C Power, Performance and Reliability in SoC Design 13:30 - 15:10	5D Designers' Forum: State-of-the-art SoCs 13:30 - 15:10
6A Advances in Modern Clock Tree Routing 15:30 - 17:10	6B Timing-related Testing and Diagnosis 15:30 - 17:10	6C Application-specific NoC Design 15:30 - 17:10	6D Designers' Forum: Is 3D Integration an Opportunity or Just a Hype? 15:30 - 17:10

Thursday, January 21, 2010

Room 101A	Room 101B	Room 101C	Room 101D
7A Modern Floorplanning and Placement Techniques 8:30 - 10:10	7B Power Optimization and Estimation in the DSM Era 8:30 - 10:10	7C Design Verification and Debugging 8:30 - 10:10	7D Special Session: Dependable Silicon Design with Unreliable Components 8:30 - 10:10
8A DFM1: Patterning and Physical Design 10:30 - 12:10	8B Design and Verification for Process Variation Issues 10:30 - 12:10	8C New Advances in High-level Synthesis 10:30 - 12:10	8D Special Session: ESL: Analysis and Synthesis of Multi-core Systems 10:30 - 12:10
9A DFM2: Variation Modeling 13:30 - 15:10	9B Power Grid Analysis 13:30 - 15:10	9C High-level Synthesis and Optimization for Performance and Power 13:30 - 15:10	9D Designers' Forum: ESL, The Road to Glory, Or Is It Not? Real Stories about Using ESL Design Methodology in Product Development 13:30 - 15:10
10A DFM3: Robust Design 15:30 - 17:10	10B Emerging Circuits and Architectures 15:30 - 17:10	10C System-level MPSoC Analysis and Optimization 15:30 - 17:10	10D Designers' Forum: Embedded Software Development for Multi-Processor Systems-on-Chip 15:30 - 17:10

List of Papers

Remark: The presenter of each paper is marked with "*".

Tuesday, January 19, 2010

Session 1K Keynote Session I
Time: 9:00 - 10:00 Tuesday, January 19, 2010
Location: Room 101
Chair: Youn-Long Lin (National Tsing Hua Univ., Taiwan)

1K-1 (Time: 9:00 - 10:00)

Title	(Keynote Address) I Attended the Nineteenth Design Automation Conference
Author	Chung-Laung Liu (National Tsing Hua Univ., Taiwan)
Detailed information (abstract, keywords, etc)

Session 2K Keynote Session II
Time: 10:20 - 11:20 Tuesday, January 19, 2010
Location: Room 101
Chair: Youn-Long Lin (National Tsing Hua Univ., Taiwan)

2K-1 (Time: 10:20 - 11:20)

Title	(Keynote Address) Delivering 10X Design Improvements
Author	Walden C. Rhines (Mentor Graphics, U.S.A.)
Detailed information (abstract, keywords, etc)

Session 3K Keynote Session III
Time: 11:20 - 12:20 Tuesday, January 19, 2010
Location: Room 101
Chair: Youn-Long Lin (National Tsing Hua Univ., Taiwan)

3K-1 (Time: 11:20 - 12:20)

Title	(Keynote Address) IC Design for the Intuitive Life Style
Author	Jim Lai (Global Unichip Corp., Taiwan)
Detailed information (abstract, keywords, etc)

Session 1A Embedded Systems Design Techniques
Time: 13:30 - 15:10 Tuesday, January 19, 2010
Location: Room 101A
Chairs: Chun Jason Xue (City Univ. of Hong Kong, Hong Kong), Tei-Wei Kuo (National Taiwan Univ., Taiwan)

1A-1 (Time: 13:30 - 13:55)

Title	A PUF Design for Secure FPGA-Based Embedded Systems
Author	*Jason H. Anderson (Univ. of Toronto, Canada)
Page	pp. 1 - 6
Detailed information (abstract, keywords, etc)
Slides

1A-2 (Time: 13:55 - 14:20)

Title	Adaptive Power Management for Real-Time Event Streams
Author	*Kai Huang (ETH Zurich, Switzerland), Luca Santinelli (Scuola Superiore Sant'Anna of Pisa, Italy), Jian-Jia Chen, Lothar Thiele (ETH Zurich, Switzerland), Giorgio C. Buttazzo (Scuola Superiore Sant'Anna of Pisa, Italy)
Page	pp. 7 - 12
Detailed information (abstract, keywords, etc)
Slides

1A-3 (Time: 14:20 - 14:45)

Title	An Alternative Polychronous Model and Synthesis Methodology for Model-Driven Embedded Software
Author	Bijoy Antony Jose, *Sandeep Kumar Shukla (FERMAT Lab, Virginia Tech, U.S.A.)
Page	pp. 13 - 18
Detailed information (abstract, keywords, etc)
Slides

1A-4 (Time: 14:45 - 15:10)

Title	Trace-based Performance Analysis Framework for Heterogeneous Multicore Systems
Author	Shih-Hao Hung, *Chia-Heng Tu, Thean-Siew Soon (National Taiwan Univ., Taiwan)
Page	pp. 19 - 24
Detailed information (abstract, keywords, etc)
Slides

Session 1B Advanced Model Order Reduction Technique
Time: 13:30 - 15:10 Tuesday, January 19, 2010
Location: Room 101B
Chairs: Hideki Asai (Shizuoka Univ., Japan), Sheldon Tan (Univ. of California, Riverside, U.S.A.)

1B-1 (Time: 13:30 - 13:55)

Title	Efficient Model Reduction of Interconnects Via Double Gramians Approximation
Author	Boyuan Yan, *Sheldon Tan (UC Riverside, U.S.A.), Gengsheng Chen (Fudan Univ., China), Yici Cai (Tsinghua Univ., China)
Page	pp. 25 - 30
Detailed information (abstract, keywords, etc)

1B-2 (Time: 13:55 - 14:20)

Title	Wideband Reduced Modeling of Interconnect Circuits by Adaptive Complex-Valued Sampling Method
Author	Hai Wang, *Sheldon Tan (UC Riverside, U.S.A.), Gengsheng Chen (Fudan Univ., China)
Page	pp. 31 - 36
Detailed information (abstract, keywords, etc)

1B-3 (Time: 14:20 - 14:45)

Title	VISA: Versatile Impulse Structure Approximation for Time-Domain Linear Macromodeling
Author	*Chi-Un Lei, Ngai Wong (Univ. of Hong Kong, Hong Kong)
Page	pp. 37 - 42
Detailed information (abstract, keywords, etc)
Slides

1B-4 (Time: 14:45 - 15:10)

Title	An Extension of the Generalized Hamiltonian Method to S-parameter Descriptor Systems
Author	*Zheng Zhang, Ngai Wong (Univ. of Hong Kong, Hong Kong)
Page	pp. 43 - 47
Detailed information (abstract, keywords, etc)

Session 1C Logic Synthesis
Time: 13:30 - 15:10 Tuesday, January 19, 2010
Location: Room 101C
Chairs: Yuan Xie (Pennsylvania State Univ., U.S.A.), Shih-Chieh Chang (National Tsing Hua Univ., Taiwan)

1C-1 (Time: 13:30 - 13:55)

Title	Simultaneous Slack Budgeting and Retiming for Synchronous Circuits Optimization
Author	*Shenghua Liu, Yuchun Ma, Xian-Long Hong, Yu Wang (Tsinghua Univ., China)
Page	pp. 49 - 54
Detailed information (abstract, keywords, etc)
Slides

1C-2 (Time: 13:55 - 14:20)

Title	A Fast SPFD-based Rewiring Technique
Author	*Pongstorn Maidee, Kia Bazargan (Univ. of Minnesota, U.S.A.)
Page	pp. 55 - 60
Detailed information (abstract, keywords, etc)
Slides

1C-3 (Time: 14:20 - 14:45)

Title	iRetILP: An Efficient Incremental Algorithm for Min-period Retiming under General Delay Model
Author	Debasish Das (Northwestern Univ., U.S.A.), Jia Wang (Illinois Inst. of Tech., U.S.A.), *Hai Zhou (Northwestern Univ., U.S.A.)
Page	pp. 61 - 67
Detailed information (abstract, keywords, etc)
Slides

Session 1D Special Session: Techniques for Efficient Energy Harvesting and Generation for Portable and Embedded Systems
Time: 13:30 - 15:10 Tuesday, January 19, 2010
Location: Room 101D
Organizer & Chair: Pai Chou (Univ. of California, Irvine/National Tsing Hua Univ., U.S.A.)

1D-1 (Time: 13:30 - 13:55)

Title	(Invited Paper) Room-Temperature Fuel Cells and Their Integration into Portable and Embedded Systems
Author	*Naehyuck Chang, Jueun Seo, Donghwa Shin, Younghyun Kim (Seoul National Univ., Republic of Korea)
Page	pp. 69 - 74
Detailed information (abstract, keywords, etc)

1D-2 (Time: 13:55 - 14:20)

Title	(Invited Paper) Maximizing the Harvested Energy for Micro-power Applications through Efficient MPPT and PMU Design
Author	Hui Shao, *Chi-Ying Tsui, Wing-Hung Ki (Hong Kong Univ. of Science and Tech., Hong Kong)
Page	pp. 75 - 80
Detailed information (abstract, keywords, etc)

1D-3 (Time: 14:20 - 14:45)

Title	(Invited Paper) Dynamic Power Management in Environmentally Powered Systems
Author	Clemens Moser, *Jian-Jia Chen, Lothar Thiele (ETH Zurich, Switzerland)
Page	pp. 81 - 88
Detailed information (abstract, keywords, etc)

1D-4 (Time: 14:45 - 15:10)

Title	(Invited Paper) Micro-scale Energy Harvesting: A System Design Perspective
Author	Chao Lu, *Vijay Raghunathan, Kaushik Roy (Purdue Univ., U.S.A.)
Page	pp. 89 - 94
Detailed information (abstract, keywords, etc)

Session 2A Memory Management and Compiler Techniques
Time: 15:30 - 17:10 Tuesday, January 19, 2010
Location: Room 101A
Chairs: Zili Shao (Hong Kong Polytechnic Univ., China), Jian-Jia Chen (ETH Zurich, Switzerland)

2A-1 (Time: 15:30 - 15:55)

Title	Co-Optimization of Memory Access and Task Scheduling on MPSoC Architectures with Multi-Level Memory
Author	Yi He (Univ. of Texas, Dallas, U.S.A.), *Chun Jason Xue (City Univ. of Hong Kong, Hong Kong), Cathy Qun Xu, Edwin Sha (Univ. of Texas, Dallas, U.S.A.)
Page	pp. 95 - 100
Detailed information (abstract, keywords, etc)
Slides

2A-2 (Time: 15:55 - 16:20)

Title	A New Compilation Technique for SIMD Code Generation across Basic Block Boundaries
Author	*Hiroaki Tanaka, Yutaka Ota, Nobu Matsumoto (Toshiba Corp., Japan), Takuji Hieda, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ., Japan)
Page	pp. 101 - 106
Detailed information (abstract, keywords, etc)
Slides

2A-3 (Time: 16:20 - 16:45)

Title	LibGALS: A Library for GALS Systems Design and Modeling
Author	*Wei-Tsun Sun, Zoran Salcic, Avinash Malik (Univ. of Auckland, New Zealand)
Page	pp. 107 - 112
Detailed information (abstract, keywords, etc)
Slides

2A-4 (Time: 16:45 - 17:10)

Title	Joint Variable Partitioning and Bank Selection Instruction Optimization on Embedded Systems with Multiple Memory Banks
Author	*Tiantian Liu, Minming Li, Chun Jason Xue (City Univ. of Hong Kong, Hong Kong)
Page	pp. 113 - 118
Detailed information (abstract, keywords, etc)
Slides

Session 2B Power and Signal Integrity
Time: 15:30 - 17:10 Tuesday, January 19, 2010
Location: Room 101B
Chairs: Yu-Min Roger Lee (National Chiao Tung Univ., Taiwan), Hsin-Po Wang (SpringSoft, Taiwan)

2B-1 (Time: 15:30 - 15:55)

Title	On-Chip Power Network Optimization with Decoupling Capacitors and Controlled-ESRs
Author	Wanping Zhang (Qualcomm Inc./UCSD, U.S.A.), Ling Zhang, Amirali Shayan (UCSD, U.S.A.), Wenjian Yu (Tsinghua Univ., China), Xiang Hu (UCSD, U.S.A.), Zhi Zhu (Qualcomm Inc., U.S.A.), Ege Engin (SDSU, U.S.A.), *Chung-Kuan Cheng (UCSD, U.S.A.)
Page	pp. 119 - 124
Detailed information (abstract, keywords, etc)
Slides

2B-2 (Time: 15:55 - 16:20)

Title	An Adaptive Parallel Flow for Power Distribution Network Simulation Using Discrete Fourier Transform
Author	Xiang Hu, Wenbo Zhao, Peng Du, Amirali Shayan, *Chung-Kuan Cheng (Univ. of California, San Diego, U.S.A.)
Page	pp. 125 - 130
Detailed information (abstract, keywords, etc)
Slides

2B-3 (Time: 16:20 - 16:45)

Title	Technique for Controlling Power-Mode Transition Noise in Distributed Sleep Transistor Network
Author	*Yongho Lee, Taewhan Kim (Seoul National Univ., Republic of Korea)
Page	pp. 131 - 136
Detailed information (abstract, keywords, etc)
Slides

2B-4 (Time: 16:45 - 17:10)

Title	A Novel FDTD Algorithm Based on Alternating-Direction Explicit Method with PML Absorbing Boundary Condition
Author	*Shuichi Aono (SESAME Technology Inc., Japan), Masaki Unno, Hideki Asai (Shizuoka Univ., Japan)
Page	pp. 137 - 141
Detailed information (abstract, keywords, etc)

Session 2C System-level Simulation
Time: 15:30 - 17:10 Tuesday, January 19, 2010
Location: Room 101C
Chairs: Chia-Lin Yang (National Taiwan Univ., Taiwan), Alan P. Su (Global Unichip Corp., Taiwan)

2C-1 (Time: 15:30 - 15:55)

Title	Speeding Up SoC Virtual Platform Simulation by Data-Dependency-Aware Synchronization and Scheduling
Author	Kuen-Huei Lin, Siao-Jie Cai, *Chung-Yang (Ric) Huang (National Taiwan Univ., Taiwan)
Page	pp. 143 - 148
Detailed information (abstract, keywords, etc)

2C-2 (Time: 15:55 - 16:20)

Title	SCGPSim: A Fast SystemC Simulator on GPUs
Author	Mahesh Nanjundappa (Virginia Polytechnic Inst. and State Univ., U.S.A.), Hiren D Patel (Univ. of Waterloo, Canada), Bijoy A Jose, *Sandeep K Shukla (Virginia Polytechnic Inst. and State Univ., U.S.A.)
Page	pp. 149 - 154
Detailed information (abstract, keywords, etc)
Slides

2C-3 (Time: 16:20 - 16:45)

Title	A Flexible Hybrid Simulation Platform Targeting Multiple Configurable Processors SoC
Author	*Hao Shen, Frédéric Pétrot (TIMA Laboratory, INP Grenoble, France)
Page	pp. 155 - 160
Detailed information (abstract, keywords, etc)
Slides

2C-4 (Time: 16:45 - 17:10)

Title	A Fast Heuristic Scheduling Algorithm for Periodic ConcurrenC Models
Author	*Weiwei Chen, Rainer Doemer (Univ. of California, Irvine, U.S.A.)
Page	pp. 161 - 166
Detailed information (abstract, keywords, etc)
Slides

Session 2D Special Session: 3D Integration and Networks on Chips
Time: 15:30 - 17:10 Tuesday, January 19, 2010
Location: Room 101D
Organizer & Moderator: Srinivasan Murali (iNoCs/EPFL, Switzerland)

2D-1 (Time: 15:30 - 15:42)

Title	(Invited Paper) Design of Networks on Chips for 3D ICs
Author	*Srinivasan Murali (iNoCs/EPFL, Switzerland), Luca Benini (Univ. of Bologna, Italy), Giovanni De Micheli (EPFL, Switzerland)
Page	pp. 167 - 168
Detailed information (abstract, keywords, etc)

2D-2 (Time: 15:42 - 17:10)

Title	(Panel Discussion) 3D Integration and Networks on Chips (Panel)
Author	Organizer & Moderator: Srinivasan Murali (iNoCs/EPFL, Switzerland), Panelists: Ruchir Puri (IBM, U.S.A.), Paull Marchal (IMEC, Belgium), Yuan Xie (Pennsylvania State Univ., U.S.A.), Ahmed Jerraya (LETI, France), Nobuaki Miyakawa (Honda Research, Japan)
Detailed information (abstract, keywords, etc)

Wednesday, January 20, 2010

Session 3A Emerging Memories and 3D ICs
Time: 8:30 - 10:10 Wednesday, January 20, 2010
Location: Room 101A
Chairs: Mehdi Baradaran Tahoori (Northeastern Univ., U.S.A.), Chin-Long Wey (National Central Univ., Taiwan)

3A-1 (Time: 8:30 - 8:55)

Title	Three-Dimensional Integrated Circuit (3D IC) Floorplan and Power/Ground Network Co-synthesis
Author	Paul Falkerstern, Yuan Xie (Pennsylvania State Univ., U.S.A.), Yao-Wen Chang (National Taiwan Univ., Taiwan), *Yu Wang (Tsinghua Univ., China)
Page	pp. 169 - 174
Detailed information (abstract, keywords, etc)

3A-2 (Time: 8:55 - 9:20)

Title	Power and Slew-aware Clock Network Design for Through-Silicon-Via (TSV) Based 3D ICs
Author	*Xin Zhao, Sung Kyu Lim (Georgia Tech, U.S.A.)
Page	pp. 175 - 180
Detailed information (abstract, keywords, etc)
Slides

3A-3 (Time: 9:20 - 9:45)

Title	A Novel Si-Tunnel FET based SRAM Design for Ultra Low-Power 0.3V V_DD Applications
Author	Jawar Singh (Univ. of Bristol, U.K.), Ramakrishnan Krishnan, Saurabh Mookerjea, Suman Datta, *Vijaykrishnan Narayanan (Pennsylvania State Univ., U.S.A.), Dhiraj Pradhan (Univ. of Bristol, U.K.)
Page	pp. 181 - 186
Detailed information (abstract, keywords, etc)

3A-4s (Time: 9:45 - 9:57)

Title	CAD Reference Flow for 3D Via-Last Integrated Circuits
Author	*Chang-Tzu Lin, Ding-Ming Kwai, Yung-Fa Chou, Ting-Sheng Chen, Wen-Ching Wu (ITRI, Taiwan)
Page	pp. 187 - 192
Detailed information (abstract, keywords, etc)
Slides

3A-5s (Time: 9:57 - 10:09)

Title	Energy and Performance Driven Circuit Design for Emerging Phase-Change Memory
Author	Dimin Niu, *Yibo Chen, Xiangyu Dong, Yuan Xie (Pennsylvania State Univ., U.S.A.)
Page	pp. 193 - 198
Detailed information (abstract, keywords, etc)

Session 3B Macromodeling and Verification of Analog Systems
Time: 8:30 - 10:10 Wednesday, January 20, 2010
Location: Room 101B
Chairs: Chin-Fong Chiu (National Chip Implementation Center, Taiwan), Eric Keiter (Sandia National Labs, U.S.A.)

3B-1 (Time: 8:30 - 8:55)

Title	Current Source Modeling in the Presence of Body Bias
Author	Saket Gupta, *Sachin S. Sapatnekar (Univ. of Minnesota, U.S.A.)
Page	pp. 199 - 204
Detailed information (abstract, keywords, etc)
Slides

3B-2 (Time: 8:55 - 9:20)

Title	Manifold Construction and Parameterization for Nonlinear Manifold-Based Model Reduction
Author	*Chenjie Gu, Jaijeet Roychowdhury (Univ. of California, Berkeley, U.S.A.)
Page	pp. 205 - 210
Detailed information (abstract, keywords, etc)
Slides

3B-3 (Time: 9:20 - 9:45)

Title	A Fast Analog Mismatch Analysis by an Incremental and Stochastic Trajectory Piecewise Linear Macromodel
Author	*Hao Yu (Berkeley Design Automation, U.S.A.), Xuexin Liu, Hai Wang, Sheldon Tan (UC Riverside, U.S.A.)
Page	pp. 211 - 216
Detailed information (abstract, keywords, etc)
Slides

3B-4 (Time: 9:45 - 10:10)

Title	Formal Verification of Tunnel Diode Oscillator with Temperature Variations
Author	*Kusum Lata, H S Jamadagni (CEDT,Indian Institute of Science, Bangalore, India)
Page	pp. 217 - 222
Detailed information (abstract, keywords, etc)

Session 3C System-level Modelling and Analysis
Time: 8:30 - 10:10 Wednesday, January 20, 2010
Location: Room 101C
Chairs: Soonhoi Ha (Seoul National Univ., Republic of Korea), Nagisa Ishiura (Kwansei Gakuin Univ., Japan)

3C-1 (Time: 8:30 - 8:55)

Title	Constrained Global Scheduling of Streaming Applications on MPSoCs
Author	*Jun Zhu, Ingo Sander, Axel Jantsch (Royal Inst. of Tech., Sweden)
Page	pp. 223 - 228
Detailed information (abstract, keywords, etc)
Slides

3C-2 (Time: 8:55 - 9:20)

Title	Analyzing Impact of Multiple ABB and AVS Domains on Throughput of Power and Thermal-Constrained Multi-Core Processors
Author	Jungseob Lee, Shi-Ting Zhou, *Nam Sung Kim (Univ. of Wisconsin-Madison, U.S.A.)
Page	pp. 229 - 234
Detailed information (abstract, keywords, etc)

3C-3 (Time: 9:20 - 9:45)

Title	Source-Level Timing Annotation for Fast and Accurate TLM Computation Model Generation
Author	Kai-Li Lin, *Chen-Kang Lo, Ren-Song Tsay (National Tsing Hua Univ., Taiwan)
Page	pp. 235 - 240
Detailed information (abstract, keywords, etc)

3C-4 (Time: 9:45 - 10:10)

Title	Improved On-Chip Router Analytical Power and Area Modeling
Author	Andrew B. Kahng, Bill Lin, *Kambiz Samadi (UC San Diego, U.S.A.)
Page	pp. 241 - 246
Detailed information (abstract, keywords, etc)
Slides

Session 3D Special Session: Recent Advancement in Post-silicon Validation
Time: 8:30 - 10:10 Wednesday, January 20, 2010
Location: Room 101D
Chair: Ing-Jer Huang (National Sun Yat-Sen Univ., Taiwan)

3D-1 (Time: 8:30 - 8:55)

Title	(Invited Paper) Data Learning Based Diagnosis
Author	*Li-C. Wang (Univ. of California, Santa Barbara, U.S.A.)
Page	pp. 247 - 254
Detailed information (abstract, keywords, etc)
Slides

3D-2 (Time: 8:55 - 9:20)

Title	(Invited Paper) Using Introspective Software-based Testing for Post-silicon Debug and Repair
Author	Todd Austin (Univ. of Michigan, U.S.A.)
Detailed information (abstract, keywords, etc)

3D-3 (Time: 9:20 - 9:45)

Title	(Invited Paper) Post-silicon Debugging for Multi-core Designs
Author	*Valeria Bertacco (Univ. of Michigan, U.S.A.)
Page	pp. 255 - 258
Detailed information (abstract, keywords, etc)

3D-4 (Time: 9:45 - 9:57)

Title	(Invited Paper) Low-cost Design for Repair with Circuit Partitioning
Author	Kyungho Kim, Byungtae Kang, Dongyun Kim (Samsung Electronics Co., Republic of Korea), Sungchul Lee, Juyong Shin, *Hyunchul Shin (Hanyang Univ., Republic of Korea)
Page	pp. 259 - 261
Detailed information (abstract, keywords, etc)

3D-5 (Time: 9:57 - 10:09)

Title	(Invited Paper) On Signal Tracing in Post-silicon Validation
Author	*Qiang Xu, Xiao Liu (Chinese Univ. of Hong Kong, Hong Kong)
Page	pp. 262 - 267
Detailed information (abstract, keywords, etc)

Session 4A New Techniques for Beyond-die Routing
Time: 10:30 - 12:10 Wednesday, January 20, 2010
Location: Room 101A
Chairs: Yasuhiro Takashima (Univ. of Kitakyushu, Japan), Yih-Lang Li (National Chiao Tung Univ., Taiwan)

4A-1 (Time: 10:30 - 10:55)

Title	CrossRouter: A Droplet Router for Cross-Referencing Digital Microfluidic Biochips
Author	*Zigang Xiao, Evangeline F.Y. Young (Chinese Univ. of Hong Kong, Hong Kong)
Page	pp. 269 - 274
Detailed information (abstract, keywords, etc)
Slides

4A-2 (Time: 10:55 - 11:20)

Title	Optimal Simultaneous Pin Assignment and Escape Routing for Dense PCBs
Author	*Hui Kong, Tan Yan, Martin D. F. Wong (Univ. of Illinois, Urbana-Champaign, U.S.A.)
Page	pp. 275 - 280
Detailed information (abstract, keywords, etc)

4A-3 (Time: 11:20 - 11:45)

Title	CAFE router: A Fast Connectivity Aware Multiple Nets Routing Algorithm for Routing Grid with Obstacles
Author	*Yukihide Kohira (Univ. of Aizu, Japan), Atsushi Takahashi (Osaka Univ., Japan)
Page	pp. 281 - 286
Detailed information (abstract, keywords, etc)

4A-4 (Time: 11:45 - 12:10)

Title	Obstacle-Aware Longest Path using Rectangular Pattern Detouring in Routing Grids
Author	Jin-Tai Yan, Ming-Ching Jhong, *Zhi-Wei Chen (Chung Hua Univ., Taiwan)
Page	pp. 287 - 292
Detailed information (abstract, keywords, etc)
Slides

Session 4B Analog Layout and Testing
Time: 10:30 - 12:10 Wednesday, January 20, 2010
Location: Room 101B
Chairs: Sachin Sapatnkar (Univ. of Minnesota, U.S.A.), Jeong-Tyng Li (SpringSoft, U.S.A.)

4B-1 (Time: 10:30 - 10:55)

Title	A Performance-Constrained Template-Based Layout Retargeting Algorithm for Analog Integrated Circuits
Author	Zheng Liu, *Lihong Zhang (Memorial Univ. of Newfoundland, Canada)
Page	pp. 293 - 298
Detailed information (abstract, keywords, etc)
Slides

4B-2 (Time: 10:55 - 11:20)

Title	Symmetry-Aware TCG-Based Placement Design under Complex Multi-Group Constraints for Analog Circuit Layouts
Author	*Rui He, Lihong Zhang (Memorial Univ. of Newfoundland, Canada)
Page	pp. 299 - 304
Detailed information (abstract, keywords, etc)
Slides

4B-3 (Time: 11:20 - 11:45)

Title	Regularity-Oriented Analog Placement with Diffusion Sharing and Well Island Generation
Author	*Shigetoshi Nakatake (Univ. of Kitakyushu, Japan), Masahiro Kawakita, Takao Ito (Toshiba Corp., Japan), Masahiro Kojima, Michiko Kojima, Kenji Izumi, Tadayuki Habasaki (NEC, Japan)
Page	pp. 305 - 311
Detailed information (abstract, keywords, etc)

4B-4 (Time: 11:45 - 12:10)

Title	A Novel Characterization Technique for High Speed I/O Mixed Signal Circuit Components Using Random Jitter Injection
Author	*Ji Hwan (Paul) Chun (Intel Corp., U.S.A.), Jae Wook Lee, Jacob A. Abraham (Univ. of Texas, Austin, U.S.A.)
Page	pp. 312 - 317
Detailed information (abstract, keywords, etc)

Session 4C New Techniques in Technology Mapping
Time: 10:30 - 12:10 Wednesday, January 20, 2010
Location: Room 101C
Chairs: Ting-Ting Hwang (National Tsing Hua Univ., Taiwan), Yuchun Ma (Tsinghua Univ., China)

4C-1 (Time: 10:30 - 10:55)

Title	Technology Mapping with Crosstalk Noise Avoidance
Author	Fang-Yu Fan (TSMC, Taiwan), *Hung-Ming Chen (NCTU, Taiwan), I-Min Liu (Atoptech, U.S.A.)
Page	pp. 319 - 324
Detailed information (abstract, keywords, etc)
Slides

4C-2 (Time: 10:55 - 11:20)

Title	Fault-Tolerant Resynthesis with Dual-Output LUTs
Author	Ju-Yueh Lee (UCLA, U.S.A.), Yu Hu (Univ. of Alberta, Canada), Rupak Majumdar, *Lei He (UCLA, U.S.A.), Minming Li (City Univ. of Hong Kong, Hong Kong)
Page	pp. 325 - 330
Detailed information (abstract, keywords, etc)
Slides

4C-3 (Time: 11:20 - 11:45)

Title	TRECO: Dynamic Technology Remapping for Timing Engineering Change Orders
Author	*Kuan-Hsien Ho, Jie-Hong Roland Jiang, Yao-Wen Chang (National Taiwan Univ., Taiwan)
Page	pp. 331 - 336
Detailed information (abstract, keywords, etc)
Slides

4C-4 (Time: 11:45 - 12:10)

Title	Multi-Operand Adder Synthesis on FPGAs Using Generalized Parallel Counters
Author	*Taeko Matsunaga, Shinji Kimura (Waseda Univ., Japan), Yusuke Matsunaga (Kyushu Univ., Japan)
Page	pp. 337 - 342
Detailed information (abstract, keywords, etc)

Session 4D University LSI Design Contest
Time: 10:30 - 12:10 Wednesday, January 20, 2010
Location: Room 101D
Organizers: Jiun-In Guo (National Chung Cheng Univ., Taiwan), Masanori Hariyama (Tohoku Univ., Japan)

4D-1 (Time: 10:30 - 10:35)

Title	Checker-Pattern and Shared Two Pixels LOFIC CMOS Image Sensors
Author	*Yoshiaki Tashiro, Shun Kawada, Shin Sakai, Shigetoshi Sugawa (Tohoku Univ., Japan)
Page	pp. 343 - 344
Detailed information (abstract, keywords, etc)
Slides

4D-2 (Time: 10:35 - 10:40)

Title	A CMOS Image Sensor With 2.0-e- Random Noise and 110-ke- Full Well Capacity Using Column Source Follower Readout Circuits
Author	*Takahiro Kohara, Wonghee Lee (Tohoku Univ., Japan), Koichi Mizobuchi (Texas Instruments Japan, Japan), Shigetoshi Sugawa (Tohoku Univ., Japan)
Page	pp. 345 - 346
Detailed information (abstract, keywords, etc)
Slides

4D-3 (Time: 10:40 - 10:45)

Title	Checkered White-RGB Color LOFIC CMOS Image Sensor
Author	*Shun Kawada, Shin Sakai, Yoshiaki Tashiro, Shigetoshi Sugawa (Tohoku Univ., Japan)
Page	pp. 347 - 348
Detailed information (abstract, keywords, etc)
Slides

4D-4 (Time: 10:45 - 10:50)

Title	A Versatile Recognition Processor for Sensor Network Applications
Author	*Risako Takashima, Hanai Yuya, Yuichi Hori, Tadahiro Kuroda (Keio Univ., Japan)
Page	pp. 349 - 350
Detailed information (abstract, keywords, etc)
Slides

4D-5 (Time: 10:50 - 10:55)

Title	A 2-6 GHz Fully Integrated Tunable CMOS Power Amplifier for Multi-Standard Transmitters
Author	Daisuke Imanishi, *JeeYoung Hong, Kenichi Okada, Akira Matsuzawa (Tokyo Inst. of Tech., Japan)
Page	pp. 351 - 352
Detailed information (abstract, keywords, etc)
Slides

4D-6 (Time: 10:55 - 11:00)

Title	An Embedded Debugging/Performance Monitoring Engine for a Tile-based 3D Graphics SoC Development
Author	*Liang-Bi Chen, Tsung-Yu Ho, Jiun-Cheng Ju, Cheng-Lung Chiang, Chung-Nan Lee, Ing-Jer Huang (National Sun Yat-Sen Univ., Taiwan)
Page	pp. 353 - 354
Detailed information (abstract, keywords, etc)
Slides

4D-7 (Time: 11:00 - 11:05)

Title	Cascaded Time Difference Amplifier using Differential Logic Delay Cell
Author	*Shingo Mandai, Toru Nakura, Makoto Ikeda, Kunihiro Asada (Univ. of Tokyo, Japan)
Page	pp. 355 - 356
Detailed information (abstract, keywords, etc)
Slides

4D-8 (Time: 11:05 - 11:10)

Title	Built-in Self At-Speed Delay Binning and Calibration Mechanism in Wireless Test Platform
Author	Chen-I Chung, Jyun-Sian Jhou, *Ching-Hwa Cheng (Feng Chia Univ., Taiwan)
Page	pp. 357 - 358
Detailed information (abstract, keywords, etc)

4D-9 (Time: 11:10 - 11:15)

Title	Dynamic Voltage Domain Assignment Technique for Low Power Performance Manageable Cell Based Design
Author	Elone Lee, Feng-Tso Chien, *Ching-Hwa Cheng (Feng Chia Univ., Taiwan), Jiun-In Guo (National Chung Cheng Univ., Taiwan)
Page	pp. 359 - 360
Detailed information (abstract, keywords, etc)

4D-10 (Time: 11:15 - 11:20)

Title	Adaptive Performance Control with Embedded Timing Error Predictive Sensors for Subthreshold Circuits
Author	*Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye (Osaka Univ., Japan)
Page	pp. 361 - 362
Detailed information (abstract, keywords, etc)
Slides

4D-12 (Time: 11:20 - 11:25)

Title	A 60GHz Direct-Conversion Transmitter in 65nm CMOS Technology
Author	*Naoki Takayama, Kouta Matsushita, Shogo Ito, Ning Li, Kenichi Okada, Akira Matsuzawa (Tokyo Inst. of Tech., Japan)
Page	pp. 363 - 364
Detailed information (abstract, keywords, etc)
Slides

4D-13 (Time: 11:25 - 11:30)

Title	An Electrically Adjustable 3-Terminal Regulator with Post-Fabrication Level-Trimming Function
Author	*Hiroyuki Morimoto, Hiroki Koike, Kazuyuki Nakamura (Kyushu Inst. of Tech., Japan)
Page	pp. 365 - 366
Detailed information (abstract, keywords, etc)

4D-14 (Time: 11:30 - 11:35)

Title	Fine Resolution Double Edge Clipping with Calibration Technique for Built-In At-Speed Delay Testing
Author	Chen-I Chung, Shuo-Wen Chang, Feng-Tso Chien, *Ching-Hwa Cheng (Feng Chia Univ., Taiwan)
Page	pp. 367 - 368
Detailed information (abstract, keywords, etc)

4D-15 (Time: 11:35 - 11:40)

Title	Geyser-1: A MIPS R3000 CPU core with fine-grained run-time Power Gating
Author	Diasuke Ikebuchi, Naomi Seki, Yuu Kojima, *Masahiro Kamata, Zhao Lei, Hideharu Amano (Keio Univ., Japan), Toshiki Shirai, Satoshi Koyama, Tatsunori Hashida, Yusuke Umahashi, Hiroki Masuda, Kimiyoshi Usami (Shibaura Inst. of Tech., Japan), Seidai Takeda, Hiroshi Nakamura (Univ. of Tokyo, Japan), Mitaro Namiki (Univ. of Agri. and Tech., Japan), Masaaki Kondo (Univ. of Electro-Communications, Japan)
Page	pp. 369 - 370
Detailed information (abstract, keywords, etc)
Slides

4D-16 (Time: 11:40 - 11:45)

Title	A WiMAX Turbo Decoder with Tailbiting BIP Architecture
Author	*Hiroaki Arai, Naoto Miyamoto, Koji Kotani (Tohoku Univ., Japan), Hisanori Fujisawa (Fujitsu Laboratories Ltd., Japan), Takashi Ito (Tohoku Univ., Japan)
Page	pp. 371 - 372
Detailed information (abstract, keywords, etc)

4D-17 (Time: 11:45 - 11:50)

Title	Temporal Circuit Partitioning for a 90nm CMOS Multi-Context FPGA and its Delay Measurement
Author	*Naoto Miyamoto, Tadahiro Ohmi (Tohoku Univ., Japan)
Page	pp. 373 - 374
Detailed information (abstract, keywords, etc)
Slides

4D-18 (Time: 11:50 - 11:55)

Title	Design and Chip Implementation of an Instruction Scheduling Free Ubiquitous Processor
Author	*Masa-aki Fukase, Ryosuke Murakami, Tomoaki Sato (Hirosaki Univ., Japan)
Page	pp. 375 - 376
Detailed information (abstract, keywords, etc)
Slides

4D-19 (Time: 11:55 - 12:00)

Title	MUCCRA-3: A Low Power Dynamically Reconfigurable Processor Array
Author	Yoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tunbunheng, Yoshihiro Yasuda, *Masayuki Kimura, Hideharu Amano (Keio Univ., Japan)
Page	pp. 377 - 378
Detailed information (abstract, keywords, etc)
Slides

4D-20 (Time: 12:00 - 12:05)

Title	Rapid Prototyping on a Structured ASIC Fabric
Author	*Steve C.L. Yuen, Yan-Qing Ai, Brian P.W. Chan, Thomas C.P. Chau, Sam M.H. Ho, Oscar K.L. Lau, Kong-Pang Pun (Chinese Univ. of Hong Kong, Hong Kong), Philip H.W. Leong (Univ. of Sydney, Australia), Oliver C.S. Choy (Chinese Univ. of Hong Kong, Hong Kong)
Page	pp. 379 - 380
Detailed information (abstract, keywords, etc)
Slides

4D-21 (Time: 12:05 - 12:10)

Title	A High Performance Low Complexity Joint Transceiver for Closed-Loop MIMO Applications
Author	Jian-Lung Tzeng, Chien-Jen Huang, *Yu-Han Yuan, Hsi-Pin Ma (National Tsing Hua Univ., Taiwan)
Page	pp. 381 - 382
Detailed information (abstract, keywords, etc)
Slides

Session 5A Clock Network Analysis and Optimization
Time: 13:30 - 15:10 Wednesday, January 20, 2010
Location: Room 101A
Chairs: Kimihiro Ogawa (STARC/Sony, Japan), Rachid Salik (Cadence Design Systems Inc., U.S.A.)

5A-1 (Time: 13:30 - 13:55)

Title	A Fast Symbolic Computation Approach to Statistical Analysis of Mesh Networks with Multiple Sources
Author	*Zhigang Hao, Guoyong Shi (Shanghai Jiaotong Univ., China)
Page	pp. 383 - 388
Detailed information (abstract, keywords, etc)
Slides

5A-2 (Time: 13:55 - 14:20)

Title	Minimizing Clock Latency Range in Robust Clock Tree Synthesis
Author	*Wen-Hao Liu, Yih-Lang Li, Hui-chi Chen (National Chiao Tung Univ., Taiwan)
Page	pp. 389 - 394
Detailed information (abstract, keywords, etc)
Slides

5A-3 (Time: 14:20 - 14:45)

Title	Blockage-Avoiding Buffered Clock-Tree Synthesis for Clock Latency-Range and Skew Minimization
Author	*Xin-Wei Shih, Chung-Chun Cheng, Yuan-Kai Ho, Yao-Wen Chang (National Taiwan Univ., Taiwan)
Page	pp. 395 - 400
Detailed information (abstract, keywords, etc)
Slides

5A-4 (Time: 14:45 - 15:10)

Title	Improved Clock-Gating Control Scheme for Transparent Pipeline
Author	*Jung Hwan Choi (Samsung Electronics, Republic of Korea), Byung Guk Kim (Purdue Univ., U.S.A.), Aurobindo Dasgupta (Intel Corp., U.S.A.), Kaushik Roy (Purdue Univ., U.S.A.)
Page	pp. 401 - 406
Detailed information (abstract, keywords, etc)
Slides

Session 5B Test Solutions for Emerging Applications
Time: 13:30 - 15:10 Wednesday, January 20, 2010
Location: Room 101B
Chairs: Wu-Tung Cheng (Mentor Graphics, U.S.A.), Ming-Der Shieh (National Cheng Kung Univ., Taiwan)

5B-1 (Time: 13:30 - 13:55)

Title	Scan-Based Attack against Elliptic Curve Cryptosystems
Author	*Ryuta Nara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ., Japan)
Page	pp. 407 - 412
Detailed information (abstract, keywords, etc)
Slides

5B-2 (Time: 13:55 - 14:20)

Title	Secure and Testable Scan Design Using Extended de Bruijn Graphs
Author	Hideo Fujiwara, *Marie Engelene J. Obien (NAIST, Japan)
Page	pp. 413 - 418
Detailed information (abstract, keywords, etc)
Slides

5B-3 (Time: 14:20 - 14:45)

Title	Correlating System Test Fmax with Structural Test Fmax and Process Monitoring Measurements
Author	*Chia-Ying (Janine) Chen (Univ. of California, Santa Barbara, U.S.A.), Jing Zeng (Advanced Micro Devices, Inc, U.S.A.), Li-C. Wang (Univ. of California, Santa Barbara, U.S.A.), Michael Mateja (Advanced Micro Devices, Inc, U.S.A.)
Page	pp. 419 - 424
Detailed information (abstract, keywords, etc)
Slides

5B-4 (Time: 14:45 - 15:10)

Title	Guided Gate-level ATPG for Sequential Circuits using a High-level Test Generation Approach
Author	*Bijan Alizadeh, Masahiro Fujita (Univ. of Tokyo, Japan)
Page	pp. 425 - 430
Detailed information (abstract, keywords, etc)
Slides

Session 5C Power, Performance and Reliability in SoC Design
Time: 13:30 - 15:10 Wednesday, January 20, 2010
Location: Room 101C
Chair: Yoshinori Takeuchi (Osaka Univ., Japan)

5C-1 (Time: 13:30 - 13:55)

Title	Optimizing Power and Performance for Reliable On-Chip Networks
Author	Aditya Yanamandra, Soumya Eachempati, Niranjan Soundararajan, *Vijaykrishnan Narayanan, Mary Jane Irwin, Ramakrishnan Krishnan (Pennsylvania State Univ., U.S.A.)
Page	pp. 431 - 436
Detailed information (abstract, keywords, etc)
Slides

5C-2 (Time: 13:55 - 14:20)

Title	A Low Latency Wormhole Router for Asynchronous On-chip Networks
Author	*Wei Song, Doug Edwards (Univ. of Manchester, U.K.)
Page	pp. 437 - 443
Detailed information (abstract, keywords, etc)
Slides

5C-3 (Time: 14:20 - 14:45)

Title	Combined Use of Rising and Falling Edge Triggered Clocks for Peak Current Reduction in IP-Based SoC Designs
Author	Tsung-Yi Wu (National Changhua Univ. of Education, Taiwan), How-Rern Lin (Providence Univ., Taiwan), Tzi-Wei Kao, *Shi-Yi Huang, Tai-Lun Li (National Changhua Univ. of Education, Taiwan)
Page	pp. 444 - 449
Detailed information (abstract, keywords, etc)
Slides

5C-4 (Time: 14:45 - 15:10)

Title	Workload Capacity Considering NBTI Degradation in Multi-core Systems
Author	Jin Sun, Roman Lysecky, Karthik Shankar (Univ. of Arizona, U.S.A.), Avinash Kodi (Ohio Univ., U.S.A.), Ahmed Louri, *Janet M. Wang (Univ. of Arizona, U.S.A.)
Page	pp. 450 - 455
Detailed information (abstract, keywords, etc)
Slides

Session 5D Designers' Forum: State-of-the-art SoCs
Time: 13:30 - 15:10 Wednesday, January 20, 2010
Location: Room 101D
Organizers: Kunio Uchiyama (Hitachi, Japan), Ing-Jer Huang (National Sun Yat-Sen Univ., Taiwan)

5D-1 (Time: 13:30 - 13:55)

Title	(Invited Paper) Overview of ITRI's Parallel Architecture Core (PAC) DSP Project: from VLIW DSP Processor to Android-ready Multicore Computing Platform
Author	*An-Yeu (Andy) Wu (STC/ITRI, Taiwan)
Detailed information (abstract, keywords, etc)

5D-2 (Time: 13:55 - 14:20)

Title	(Invited Paper) Design and Verification Methods of Toshiba's Wireless LAN Baseband SoC
Author	*Masanori Kuwahara (Toshiba, Japan)
Page	pp. 457 - 463
Detailed information (abstract, keywords, etc)
Slides

5D-3 (Time: 14:20 - 14:45)

Title	(Invited Paper) Programmable Platform for Multimedia SoC
Author	*Bor-Sung Liang (Sunplus Core Technology, Taiwan)
Detailed information (abstract, keywords, etc)

5D-4 (Time: 14:45 - 15:10)

Title	(Invited Paper) SOC for Car Navigation Systems with a 55.3 GOPS Image Recognition Engine
Author	*Hiroyuki Hamasaki, Yasuhiko Hoshi, Atsushi Nakamura, Akihiro Yamamoto (Renesas, Japan), Hideaki Kido, Shoji Muramatsu (Hitachi Ltd, Japan)
Page	pp. 464 - 465
Detailed information (abstract, keywords, etc)
Slides

Session 6A Advances in Modern Clock Tree Routing
Time: 15:30 - 17:10 Wednesday, January 20, 2010
Location: Room 101A
Chairs: Martin D. F. Wong (Univ. of Illinois, Urbana-Champaign, U.S.A.), Tsung-Yi Ho (National Cheng Kung Univ., Taiwan)

6A-1 (Time: 15:30 - 15:55)

Title	A Dual-MST Approach for Clock Network Synthesis
Author	*Jingwei Lu, Wing-Kai Chow, Chiu-Wing Sham (Hong Kong Polytechnic Univ., Hong Kong), Fung-Yu Young (Chinese Univ. of Hong Kong, Hong Kong)
Page	pp. 467 - 473
Detailed information (abstract, keywords, etc)
Slides

6A-2 (Time: 15:55 - 16:20)

Title	Buffered Clock Tree Sizing for Skew Minimization Under Power and Thermal Budgets
Author	Krit Athikulwongse, *Xin Zhao, Sung Kyu Lim (Georgia Tech, U.S.A.)
Page	pp. 474 - 479
Detailed information (abstract, keywords, etc)
Slides

6A-3 (Time: 16:20 - 16:45)

Title	Critical-PMOS-Aware Clock Tree Design Methodology for Anti-Aging Zero Skew Clock Gating
Author	Shih-Hsu Huang, Chia-Ming Chang, *Wen-Pin Tu, Song-Bin Pan (Chung Yuan Christian Univ., Taiwan)
Page	pp. 480 - 485
Detailed information (abstract, keywords, etc)
Slides

6A-4 (Time: 16:45 - 17:10)

Title	Clock Tree Embedding for 3D ICs
Author	*Tak-Yung Kim, Taewhan Kim (Seoul National Univ., Republic of Korea)
Page	pp. 486 - 491
Detailed information (abstract, keywords, etc)
Slides

Session 6B Timing-related Testing and Diagnosis
Time: 15:30 - 17:10 Wednesday, January 20, 2010
Location: Room 101B
Chairs: Shi-Yu Huang (National Tsing Hua Univ., Taiwan), Hideo Fujiwara (NAIST, Japan)

6B-1 (Time: 15:30 - 15:55)

Title	Improved Weight Assignment for Logic Switching Activity During At-Speed Test Pattern Generation
Author	*Meng-Fan Wu, Hsin-Chieh Pan, Teng-Han Wang, Jiun-Lang Huang (National Taiwan Univ., Taiwan), Kun-Han Tsai, Wu-Tung Cheng (Mentor Graphics Corp., U.S.A.)
Page	pp. 493 - 498
Detailed information (abstract, keywords, etc)
Slides

6B-2 (Time: 15:55 - 16:20)

Title	Graph Partition based Path Selection for Testing of Small Delay Defects
Author	Zijian He, *Tao Lv, Huawei Li, Xiaowei Li (Institute of Computing Technology, CAS, China)
Page	pp. 499 - 504
Detailed information (abstract, keywords, etc)
Slides

6B-3 (Time: 16:20 - 16:45)

Title	Functional and Partially-Functional Skewed-Load Tests
Author	Irith Pomeranz (Purdue Univ., U.S.A.), *Sudhakar M. Reddy (Univ. of Iowa, U.S.A.)
Page	pp. 505 - 510
Detailed information (abstract, keywords, etc)
Slides

6B-4 (Time: 16:45 - 17:10)

Title	Emulating and Diagnosing IR-Drop by Using Dynamic SDF
Author	Ke Peng (Univ. of Connecticut, U.S.A.), Yu Huang, Ruifeng Guo, *Wu-Tung Cheng (Mentor Graphics, U.S.A.), Mohammad Tehranipoor (Univ. of Connecticut, U.S.A.)
Page	pp. 511 - 516
Detailed information (abstract, keywords, etc)
Slides

Session 6C Application-specific NoC Design
Time: 15:30 - 17:10 Wednesday, January 20, 2010
Location: Room 101C
Chairs: Michihiro Koibuchi (NII, Japan), Samar Abdi (Concordia Univ., Canada)

6C-1 (Time: 15:30 - 15:55)

Title	Application-Specific 3D Network-on-Chip Design Using Simulated Allocation
Author	Pingqiang Zhou (Univ. of Minnesota, U.S.A.), Ping-Hung Yuh (National Taiwan Univ., Taiwan), *Sachin S. Sapatnekar (Univ. of Minnesota, U.S.A.)
Page	pp. 517 - 522
Detailed information (abstract, keywords, etc)
Slides

6C-2 (Time: 15:55 - 16:20)

Title	A3MAP: Architecture-Aware Analytic Mapping for Networks-on-Chip
Author	Wooyoung Jang, *David Z. Pan (Univ. of Texas, Austin, U.S.A.)
Page	pp. 523 - 528
Detailed information (abstract, keywords, etc)
Slides

6C-3 (Time: 16:20 - 16:45)

Title	Efficient Throughput-Guarantees for Latency-Sensitive Networks-On-Chip
Author	*Jonas Diemer, Rolf Ernst (Institute of Computer and Network Engineering, TU Braunschweig, Germany), Michael Kauschke (Intel, Germany)
Page	pp. 529 - 534
Detailed information (abstract, keywords, etc)
Slides

6C-4 (Time: 16:45 - 17:10)

Title	Floorplanning and Topology Generation for Application-Specific Network-on-Chip
Author	*Bei Yu, Sheqin Dong (Tsinghua Univ., China), Song Chen, Satoshi Goto (Waseda Univ., Japan)
Page	pp. 535 - 540
Detailed information (abstract, keywords, etc)
Slides

Session 6D Designers' Forum: Is 3D Integration an Opportunity or Just a Hype?
Time: 15:30 - 17:10 Wednesday, January 20, 2010
Location: Room 101D
Organizers: Cheng-Wen Wu (National Tsing Hua Univ./ITRI, Taiwan), Jin-Fu Li (National Central Univ./ITRI, Taiwan)

6D-1 (Time: 15:30 - 15:55)

Title	(Invited Paper) (Tutorial) Is 3D Integration an Opportunity or Just a Hype?
Author	*Jin-Fu Li (National Central Univ./ITRI, Taiwan), Cheng-Wen Wu (Tsing-Hua Univ., Taiwan)
Page	pp. 541 - 543
Detailed information (abstract, keywords, etc)
Slides

6D-2 (Time: 15:55 - 17:10)

Title	(Panel Discussion) (Panel) Is 3D Integration an Opportunity or Just a Hype?
Author	Organizers & Moderators: Cheng-Wen Wu (National Tsing Hua Univ./ITRI, Taiwan), Jin-Fu Li (National Central Univ./ITRI, Taiwan), Panelists: Albert Li (GUC, Taiwan), Erik Jan Marinissen (IMEC, Belgium), Ding-Ming Kwai (ITRI, Taiwan), Kyu-Myung Choi (Samsung, Republic of Korea), Makoto Takahashi (Toshiba, Japan)
Page	pp. 544 - 547
Detailed information (abstract, keywords, etc)

Thursday, January 21, 2010

Session 7A Modern Floorplanning and Placement Techniques
Time: 8:30 - 10:10 Thursday, January 21, 2010
Location: Room 101A
Chairs: David Pan (Univ. of Texas, Austin, U.S.A.), Hung-Ming Chen (National Chiao Tung Univ., Taiwan)

7A-1 (Time: 8:30 - 8:55)

Title	Configurable Multi-product Floorplanning
Author	Qiang Ma, *Martin D. F. Wong (Univ. of Illinois, Urbana-Champaign, U.S.A.), Kai-Yuan Chao (Intel Corp., U.S.A.)
Page	pp. 549 - 554
Detailed information (abstract, keywords, etc)
Slides

7A-2 (Time: 8:55 - 9:20)

Title	UFO: Unified Convex Optimization Algorithms for Fixed-Outline Floorplanning
Author	*Jai-Ming Lin, Hsi Hung (National Cheng Kung Univ., Taiwan)
Page	pp. 555 - 560
Detailed information (abstract, keywords, etc)
Slides

7A-3 (Time: 9:20 - 9:45)

Title	Fixed-outline Thermal-aware 3D Floorplanning
Author	*Linfu Xiao (Chinese Univ. of Hong Kong, Hong Kong), Subarna Sinha (Synopsys, U.S.A.), Jingyu Xu (Synopsys, China), Evangeline F.Y. Young (Chinese Univ. of Hong Kong, Hong Kong)
Page	pp. 561 - 567
Detailed information (abstract, keywords, etc)
Slides

7A-4 (Time: 9:45 - 10:10)

Title	A Hierarchical Bin-Based Legalizer for Standard-Cell Designs with Minimal Disturbance
Author	Yu-Min Lee, *Tsung-You Wu, Po-Yi Chiang (National Chiao Tung Univ., Taiwan)
Page	pp. 568 - 573
Detailed information (abstract, keywords, etc)
Slides

Session 7B Power Optimization and Estimation in the DSM Era
Time: 8:30 - 10:10 Thursday, January 21, 2010
Location: Room 101B
Chairs: Kimiyoshi Usami (Shibaura Inst. of Tech., Japan), Masanori Hashimoto (Osaka Univ., Japan)

7B-1 (Time: 8:30 - 8:55)

Title	An Analytical Dynamic Scaling of Supply Voltage and Body Bias Exploiting Memory Stall Time Variation
Author	*Jungsoo Kim, Younghoon Lee (KAIST, Republic of Korea), Sungjoo Yoo (POSTECH, Republic of Korea), Chong-Min Kyung (KAIST, Republic of Korea)
Page	pp. 575 - 580
Detailed information (abstract, keywords, etc)
Slides

7B-2 (Time: 8:55 - 9:20)

Title	Bounded Potential Slack: Enabling Time Budgeting for Dual-Vt Allocation of Hierarchical Design
Author	*Jun Seomun, Seungwhun Paik, Youngsoo Shin (KAIST, Republic of Korea)
Page	pp. 581 - 586
Detailed information (abstract, keywords, etc)
Slides

7B-3 (Time: 9:20 - 9:45)

Title	Dynamic Power Estimation for Deep Submicron Circuits with Process Variation
Author	Quang Dinh, *Deming Chen, Martin Wong (UIUC, U.S.A.)
Page	pp. 587 - 592
Detailed information (abstract, keywords, etc)
Slides

7B-4 (Time: 9:45 - 10:10)

Title	Runtime Temperature-Based Power Estimation for Optimizing Throughput of Thermal-Constrained Multi-Core Processors
Author	Dongkeun Oh, Nam Sung Kim, Yu Hen Hu (Univ. of Wisconsin, U.S.A.), *Charlie Chung Ping Chen (National Taiwan Univ., Taiwan), Azadeh Davoodi (Univ. of Wisconsin, U.S.A.)
Page	pp. 593 - 599
Detailed information (abstract, keywords, etc)

Session 7C Design Verification and Debugging
Time: 8:30 - 10:10 Thursday, January 21, 2010
Location: Room 101C
Chairs: Yirng-An Chen (Marvell Corp., U.S.A.), Jie-Hong (Roland) Jiang (National Taiwan Univ., Taiwan)

7C-1 (Time: 8:30 - 8:55)

Title	Managing Verification Error Traces with Bounded Model Debugging
Author	*Sean Safarpour (Vennsa Technologies, Canada), Andreas Veneris, Farid Najm (Univ. of Toronto, Canada)
Page	pp. 601 - 606
Detailed information (abstract, keywords, etc)
Slides

7C-2 (Time: 8:55 - 9:20)

Title	Automatic Assertion Extraction via Sequential Data Mining of Simulation Traces
Author	*Po-Hsien Chang, Li-C. Wang (Univ. of California, Santa Barbara, U.S.A.)
Page	pp. 607 - 612
Detailed information (abstract, keywords, etc)

7C-3 (Time: 9:20 - 9:45)

Title	Automatic Constraint Generation for Guided Random Simulation
Author	*Hu-Hsi Yeh, Chung-Yang (Ric) Huang (National Taiwan Univ., Taiwan)
Page	pp. 613 - 618
Detailed information (abstract, keywords, etc)

7C-4 (Time: 9:45 - 10:10)

Title	A Method for Debugging of Pipelined Processors in Formal Verification by Correspondence Checking
Author	*Miroslav Velev, Ping Gao (Aries Design Automation, U.S.A.)
Page	pp. 619 - 624
Detailed information (abstract, keywords, etc)

Session 7D Special Session: Dependable Silicon Design with Unreliable Components
Time: 8:30 - 10:10 Thursday, January 21, 2010
Location: Room 101D
Organizer & Moderator: Vincent Mooney (Georgia Tech/Nanyang Technological Univ., U.S.A.)

7D-1 (Time: 8:30 - 8:55)

Title	(Invited Paper) Resilient Design in Scaled CMOS for Energy Efficiency
Author	James Tschanz, Keith Bowman, Muhammad Khellah, Chris Wilkerson, Bibiche Geuskens, Dinesh Somasekhar, Arijit Raychowdhury, Jaydeep Kulkarni, Carlos Tokunaga, Shih-Lien Lu, Tanay Karnik, *Vivek K. De (Intel Corp., U.S.A.)
Page	p. 625
Detailed information (abstract, keywords, etc)
Slides

7D-2 (Time: 8:55 - 9:20)

Title	(Invited Paper) Benefits and Barriers to Probabilistic Design
Author	*Siva Narendra (Tyfone, Inc./Portland State Univ., U.S.A.)
Page	pp. 626 - 627
Detailed information (abstract, keywords, etc)

7D-3 (Time: 9:20 - 9:45)

Title	(Invited Paper) A Probabilistic Boolean Logic for Energy Efficient Circuit and System Design
Author	Lakshmi N. B. Chakrapani (Rice Univ., U.S.A.), *Krishna Palem (Rice Univ./Nanyang Technological Univ., U.S.A.)
Page	pp. 628 - 635
Detailed information (abstract, keywords, etc)

7D-4 (Time: 9:45 - 10:10)

Title	(Panel Discussion) Dependable Silicon Design with Unreliable Components
Author	Organizer & Moderator: Vincent Mooney (Georgia Tech/Nanyang Technological Univ., U.S.A.), Panelists: Vivek K. De (Intel Corp., U.S.A.), Siva Narendra (Tyfone, Inc., U.S.A.), Krishna Palem (Rice Univ./Nanyang Technological Univ., U.S.A.)
Detailed information (abstract, keywords, etc)

Session 8A DFM1: Patterning and Physical Design
Time: 10:30 - 12:10 Thursday, January 21, 2010
Location: Room 101A
Chairs: Fedor G. Pikus (Mentor Graphics Corp., U.S.A.), Masanori Hashimoto (Osaka Univ., Japan)

8A-1 (Time: 10:30 - 10:55)

Title	A New Graph-theoretic, Multi-objective Layout Decomposition Framework for Double Patterning Lithography
Author	*Jae-Seok Yang (Univ. of Texas, Austin, U.S.A.), Katrina Lu (Intel, U.S.A.), MinSik Cho (IBM Research, U.S.A.), Kun Yuan, David Z. Pan (Univ. of Texas, Austin, U.S.A.)
Page	pp. 637 - 644
Detailed information (abstract, keywords, etc)
Slides

8A-2 (Time: 10:55 - 11:20)

Title	A Robust Pixel-Based RET Optimization Algorithm Independent of Initial Conditions
Author	*Jinyu Zhang (Tsinghua Univ., China), Min-Chun Tsai (Brion Technology, U.S.A.), Wei Xiong, Yan Wang, Zhiping Yu (Tsinghua Univ., China)
Page	pp. 645 - 650
Detailed information (abstract, keywords, etc)

8A-3 (Time: 11:20 - 11:45)

Title	A New Method to Improve Accuracy of Parasitics Extraction Considering Sub-wavelength Lithography Effects
Author	*Kuen-Yu Tsai, Wei-Jhih Hsieh, Yuan-Ching Lu, Bo-Sen Chang, Sheng-Wei Chien, Yi-Chang Lu (National Taiwan Univ., Taiwan)
Page	pp. 651 - 656
Detailed information (abstract, keywords, etc)
Slides

8A-4 (Time: 11:45 - 12:10)

Title	Dead Via Minimization by Simultaneous Routing and Redundant Via Insertion
Author	*Chih-Ta Lin, Yen-Hung Lin, Guan-Chan Su, Yih-Lang Li (National Chiao Tung Univ., Taiwan)
Page	pp. 657 - 662
Detailed information (abstract, keywords, etc)

Session 8B Design and Verification for Process Variation Issues
Time: 10:30 - 12:10 Thursday, January 21, 2010
Location: Room 101B
Chairs: Shih-Hsu Huang (Chung Yuan Christian Univ., Taiwan), Atsushi Takahashi (Osaka Univ., Japan)

8B-1 (Time: 10:30 - 10:55)

Title	Statistical Timing Verification for Transparently Latched Circuits through Structural Graph Traversal
Author	*Xingliang Yuan, Jia Wang (Illinois Inst. of Tech., U.S.A.)
Page	pp. 663 - 668
Detailed information (abstract, keywords, etc)
Slides

8B-2 (Time: 10:55 - 11:20)

Title	A Unified Multi-Corner Multi-Mode Static Timing Analysis Engine
Author	Jing Jia Nian, *Shih Heng Tsai, Chung Yang (Ric) Huang (National Taiwan Univ., Taiwan)
Page	pp. 669 - 674
Detailed information (abstract, keywords, etc)
Slides

8B-3 (Time: 11:20 - 11:45)

Title	Statistical Time Borrowing for Pulsed-Latch Circuit Designs
Author	*Seungwhun Paik, Lee-eun Yu, Youngsoo Shin (KAIST, Republic of Korea)
Page	pp. 675 - 680
Detailed information (abstract, keywords, etc)

8B-4 (Time: 11:45 - 12:10)

Title	Design Time Body Bias Selection for Parametric Yield Improvement
Author	*Cheng Zhuo, Yung-Hsu Chang, Dennis Sylvester, David Blaauw (Univ. of Michigan, Ann Arbor, U.S.A.)
Page	pp. 681 - 688
Detailed information (abstract, keywords, etc)

Session 8C New Advances in High-level Synthesis
Time: 10:30 - 12:10 Thursday, January 21, 2010
Location: Room 101C
Chairs: Taewhan Kim (Seoul National Univ., Republic of Korea), Yusuke Matsunaga (Kyushu Univ., Japan)

8C-1 (Time: 10:30 - 10:55)

Title	Minimizing Leakage Power in Aging-Bounded High-level Synthesis with Design Time Multi-Vth Assignment
Author	*Yibo Chen (Penn State Univ., U.S.A.), Yu Wang (Tsinghua Univ., China), Yuan Xie (Penn State Univ., U.S.A.), Andres Takach (Mentor Graphics Corp., U.S.A.)
Page	pp. 689 - 694
Detailed information (abstract, keywords, etc)

8C-2 (Time: 10:55 - 11:20)

Title	A Global Interconnect Reduction Technique during High Level Synthesis
Author	Taemin Kim (Univ. of California, Los Angeles, U.S.A.), *Xun Liu (North Carolina State Univ., U.S.A.)
Page	pp. 695 - 700
Detailed information (abstract, keywords, etc)
Slides

8C-3 (Time: 11:20 - 11:45)

Title	Incremental High-Level Synthesis
Author	Luciano Lavagno (Cadence Design Systems, U.S.A.), Mototsugu Fujii (Renesas Technology Corp., Japan), Alex Kondratyev (Cadence Design Systems, U.S.A.), Noriyasu Nakayama (Fujitsu Advanced Technologies, Japan), Mitsuru Tatesawa (Renesas Technology Corp., Japan), Yosinori Watanabe (Cadence Design Systems, U.S.A.), *Qiang Zhu (Cadence Design Systems, Japan)
Page	pp. 701 - 706
Detailed information (abstract, keywords, etc)

8C-4 (Time: 11:45 - 12:10)

Title	A High-Level Synthesis Flow for Custom Instruction Set Extensions for Application-Specific Processors
Author	Nagaraju Pothineni (Google, India, India), *Philip Brisk, Paolo Ienne (EPFL, Switzerland), Anshul Kumar, Kolin Paul (Indian Inst. of Tech., Delhi, India)
Page	pp. 707 - 712
Detailed information (abstract, keywords, etc)
Slides

Session 8D Special Session: ESL: Analysis and Synthesis of Multi-core Systems
Time: 10:30 - 12:10 Thursday, January 21, 2010
Location: Room 101D
Organizer & Chair: Daniel D. Gajski (Univ. of California, Irvine, U.S.A.)

8D-1 (Time: 10:30 - 10:55)

Title	(Invited Paper) Computer-aided Recoding for Multi-core Systems
Author	*Rainer Doemer (Univ. of California, Irvine, U.S.A.)
Page	pp. 713 - 716
Detailed information (abstract, keywords, etc)
Slides

8D-2 (Time: 10:55 - 11:20)

Title	(Invited Paper) TLM Automation for Multi-core Design
Author	*Samar Abdi (Concordia Univ., Canada)
Page	pp. 717 - 724
Detailed information (abstract, keywords, etc)
Slides

8D-3 (Time: 11:20 - 11:45)

Title	(Invited Paper) Platform Modeling for Exploration and Synthesis
Author	*Andreas Gerstlauer (Univ. of Texas, Austin, U.S.A.), Gunar Schirner (Northeastern Univ., Boston, U.S.A.)
Page	pp. 725 - 731
Detailed information (abstract, keywords, etc)
Slides

8D-4 (Time: 11:45 - 12:10)

Title	(Invited Paper) Application of ESL Synthesis on GSM Edge Algorithm for Base Station
Author	*Alan P. Su (Global Unichip, Taiwan)
Page	pp. 732 - 737
Detailed information (abstract, keywords, etc)
Slides

Session 9A DFM2: Variation Modeling
Time: 13:30 - 15:10 Thursday, January 21, 2010
Location: Room 101A
Chairs: Keh-Jeng Chang (National Tsing Hua Univ., Taiwan), Jing-Jou Tang (Southern Taiwan Univ., Taiwan)

9A-1 (Time: 13:30 - 13:55)

Title	Analyzing Electrical Effects of RTA-driven Local Anneal Temperature Variation
Author	*Vivek Joshi (Univ. of Michigan, U.S.A.), Kanak Agarwal (IBM, U.S.A.), Dennis Sylvester, David Blaauw (Univ. of Michigan, U.S.A.)
Page	pp. 739 - 744
Detailed information (abstract, keywords, etc)
Slides

9A-2 (Time: 13:55 - 14:20)

Title	Physical Design Techniques for Optimizing RTA-induced Variations
Author	Yaoguang Wei (Univ. of Minnesota, U.S.A.), Jiang Hu (Texas A&M Univ., U.S.A.), Frank Liu (IBM, U.S.A.), *Sachin Sapatnekar (Univ. of Minnesota, U.S.A.)
Page	pp. 745 - 750
Detailed information (abstract, keywords, etc)
Slides

9A-3 (Time: 14:20 - 14:45)

Title	On Confidence in Characterization and Application of Variation Models
Author	Lerong Cheng, Puneet Gupta, *Lei He (UCLA, U.S.A.)
Page	pp. 751 - 756
Detailed information (abstract, keywords, etc)

Session 9B Power Grid Analysis
Time: 13:30 - 15:10 Thursday, January 21, 2010
Location: Room 101B
Chairs: Youngsoo Shin (KAIST, Republic of Korea), Nam Sung Kim (Univ. of Wisconsin-Madison, U.S.A.)

9B-1 (Time: 13:30 - 13:55)

Title	Incremental Solution of Power Grids using Random Walks
Author	*Baktash Boghrati, Sachin S. Sapatnekar (Univ. of Minnesota, U.S.A.)
Page	pp. 757 - 762
Detailed information (abstract, keywords, etc)
Slides

9B-2 (Time: 13:55 - 14:20)

Title	Efficient Power Grid Integrity Analysis Using On-the-Fly Error Check and Reduction
Author	Duo Li, *Sheldon Tan, Ning Mi (Univ. of California, Riverside, U.S.A.), Yici Cai (Tsinghua Univ., China)
Page	pp. 763 - 768
Detailed information (abstract, keywords, etc)

9B-3 (Time: 14:20 - 14:45)

Title	PS-FPG: Pattern Selection based co-design of Floorplan and Power/Ground Network with Wiring Resource Optimization
Author	Li Li (WuHan Univ. of Tech., China), *Yuchun Ma (Tsinghua Univ., China), Ning Xu (WuHan Univ. of Tech., China), Yu Wang, Xianlong Hong (Tsinghua Univ., China)
Page	pp. 769 - 774
Detailed information (abstract, keywords, etc)

9B-4 (Time: 14:45 - 15:10)

Title	Gate Delay Estimation in STA under Dynamic Power Supply Noise
Author	*Takaaki Okumura, Fumihiro Minami, Kenji Shimazaki, Kimihiko Kuwada (STARC, Japan), Masanori Hashimoto (Osaka Univ., Japan)
Page	pp. 775 - 780
Detailed information (abstract, keywords, etc)
Slides

Session 9C High-level Synthesis and Optimization for Performance and Power
Time: 13:30 - 15:10 Thursday, January 21, 2010
Location: Room 101C
Chairs: Lih-Yih Chiou (National Cheng Kung Univ., Taiwan), Jen-Chieh Yeh (ITRI, Taiwan)

9C-1 (Time: 13:30 - 13:55)

Title	Parametric Yield Driven Resource Binding in Behavioral Synthesis with Multi-Vth/Vdd Library
Author	*Yibo Chen (Penn State Univ., U.S.A.), Yu Wang (Tsinghua Univ., China), Yuan Xie (Penn State Univ., U.S.A.), Andres Takach (Mentor Graphics Corp., U.S.A.)
Page	pp. 781 - 786
Detailed information (abstract, keywords, etc)
Slides

9C-2 (Time: 13:55 - 14:20)

Title	Optimizing Blocks in an SoC Using Symbolic Code-Statement Reachability Analysis
Author	*Hong-Zu Chou (National Taiwan Univ., Taiwan), Kai-Hui Chang (Avery Design Systems, U.S.A.), Sy-Yen Kuo (National Taiwan Univ., Taiwan)
Page	pp. 787 - 792
Detailed information (abstract, keywords, etc)
Slides

9C-3 (Time: 14:20 - 14:45)

Title	High Level Event Driven Thermal Estimation for Thermal Aware Task Allocation and Scheduling
Author	*Jin Cui, Douglas L. Maskell (Nanyang Technological Univ., Singapore)
Page	pp. 793 - 798
Detailed information (abstract, keywords, etc)
Slides

9C-4 (Time: 14:45 - 15:10)

Title	Mapping and Scheduling of Parallel C Applications with Ant Colony Optimization onto Heterogeneous Reconfigurable MPSoCs
Author	Fabrizio Ferrandi, *Christian Pilato, Donatella Sciuto, Antonino Tumeo (Politecnico di Milano, Italy)
Page	pp. 799 - 804
Detailed information (abstract, keywords, etc)
Slides

Session 9D Designers' Forum: ESL, The Road to Glory, Or Is It Not? Real Stories about Using ESL Design Methodology in Product Development
Time: 13:30 - 15:10 Thursday, January 21, 2010
Location: Room 101D
Organizers: Alan P. Su (Global Unichip Corp., Taiwan), Ing-Jer Huang (National Sun Yat-Sen Univ., Taiwan)

9D-1 (Time: 13:30 - 13:55)

Title	(Invited Paper) -Possibility of ESL- A Software Centric System Design for Multicore SoC in the Upstream Phase
Author	*Koichiro Yamashita (Fujitsu Laboratories Ltd., Japan)
Page	pp. 805 - 808
Detailed information (abstract, keywords, etc)
Slides

9D-2 (Time: 13:55 - 14:20)

Title	(Invited Paper) Design of Complex Image Processing Systems in ESL
Author	Benjamin Carrion Schafer (NEC Corp., Japan), Ashish Trambadia (NEC, Japan), *Kazutoshi Wakabayashi (NEC Corp., Japan)
Page	pp. 809 - 814
Detailed information (abstract, keywords, etc)

9D-3 (Time: 14:20 - 14:45)

Title	(Invited Paper) PAC Duo System Power Estimation at ESL
Author	*Wen-Tsan Hsieh, Jen-Chieh Yeh (ITRI, Taiwan), Shi-Yu Huang (TinnoTek Corp./National Tsing Hua Univ., Taiwan)
Page	pp. 815 - 820
Detailed information (abstract, keywords, etc)

9D-4 (Time: 14:45 - 15:10)

Title	(Invited Paper) A Practice of ESL Verification Methodology from SystemC to FPGA -Using EPC Class-1 Generation-2 RFID Tag Design as An Example
Author	*William Young (TSMC, Taiwan), Chua-Huang Huang (Feng Chia Univ., Taiwan), Alan P. Su (Global Unichip Corp., Taiwan), C. P. Jou, Fu-Lung Hsueh (TSMC, Taiwan)
Page	pp. 821 - 824
Detailed information (abstract, keywords, etc)
Slides

Session 10A DFM3: Robust Design
Time: 15:30 - 17:10 Thursday, January 21, 2010
Location: Room 101A
Chairs: Toshiyuki Shibuya (Fujitsu Laboratories of America, Inc, U.S.A.), Yi Chang Lu (National Taiwan Univ., Taiwan)

10A-1 (Time: 15:30 - 15:55)

Title	Slack Redistribution for Graceful Degradation Under Voltage Overscaling
Author	Andrew B. Kahng, *Seokhyeong Kang (UC San Diego, U.S.A.), Rakesh Kumar, John Sartori (UIUC, U.S.A.)
Page	pp. 825 - 831
Detailed information (abstract, keywords, etc)
Slides

10A-2 (Time: 15:55 - 16:20)

Title	A Decoder-Based Switch Box to Mitigate Soft Errors in SRAM-Based FPGAs
Author	*Hassan Ebrahimi, Morteza Zamani, HamidReza Zarandi (Amirkabir, Iran)
Page	pp. 832 - 837
Detailed information (abstract, keywords, etc)

10A-3s (Time: 16:20 - 16:32)

Title	On Process-Aware 1-D Standard Cell Design
Author	Hongbo Zhang, *Martin D. F. Wong (Univ. of Illinois, Urbana-Champaign, U.S.A.), Kai-Yuan Chao (Intel Corp., U.S.A.)
Page	pp. 838 - 842
Detailed information (abstract, keywords, etc)

10A-4s (Time: 16:32 - 16:44)

Title	D-A Converter Based Variation Analysis for Analog Layout Design
Author	*Bo Liu, Toru Fujimura, Bo Yang, Shigetoshi Nakatake (Univ. of Kitakyushu, Japan)
Page	pp. 843 - 848
Detailed information (abstract, keywords, etc)
Slides

Session 10B Emerging Circuits and Architectures
Time: 15:30 - 17:10 Thursday, January 21, 2010
Location: Room 101B
Chairs: Xiaoyang Zeng (Fudan Univ., China), Chun-Ming Huang (National Chip Implementation Center, Taiwan)

10B-1 (Time: 15:30 - 15:55)

Title	Rule-Based Optimization of Reversible Circuits
Author	*Mona Arabzadeh, Mehdi Saeedi, Morteza Saheb Zamani (Amirkabir Univ. of Tech., Iran)
Page	pp. 849 - 854
Detailed information (abstract, keywords, etc)
Slides

10B-2 (Time: 15:55 - 16:20)

Title	Variation Tolerant Logic Mapping for Crossbar Array Nano Architectures
Author	Cihan Tunc (Northeastern Univ., U.S.A.), *Mehdi Tahoori (Northeastern Univ./Karlsruhe Inst. of Tech., U.S.A.)
Page	pp. 855 - 860
Detailed information (abstract, keywords, etc)
Slides

10B-3 (Time: 16:20 - 16:45)

Title	Generalised Threshold Gate Synthesis based on AND/OR/NOT Representation of Boolean Function
Author	*Marek Arkadiusz Bawiec, Maciej Nikodem (Wrocław Univ. of Tech., Poland)
Page	pp. 861 - 866
Detailed information (abstract, keywords, etc)
Slides

10B-4 (Time: 16:45 - 17:10)

Title	Novel Dual-vth Independent-gate FinFET Circuits
Author	Masoud Rostami, *Kartik Mohanram (Rice Univ., U.S.A.)
Page	pp. 867 - 872
Detailed information (abstract, keywords, etc)

Session 10C System-level MPSoC Analysis and Optimization
Time: 15:30 - 17:10 Thursday, January 21, 2010
Location: Room 101C
Chairs: Yuichi Nakamura (NEC Corp., Japan), Lovic Gauthier (Kyusyu Univ., Japan)

10C-1 (Time: 15:30 - 15:55)

Title	Hybrid Dynamic Energy and Thermal Management in Heterogeneous Embedded Multiprocessor SoCs
Author	Shervin Sharifi, Ayse Kivilcim Coskun, *Tajana Simunic Rosing (Univ. of California, San Diego, U.S.A.)
Page	pp. 873 - 878
Detailed information (abstract, keywords, etc)
Slides

10C-2 (Time: 15:55 - 16:20)

Title	Energy Efficient Joint Scheduling and Multi-core Interconnect Design
Author	Cathy Qun Xu (Univ. of Texas, Dallas, U.S.A.), *Chun Jason Xue (City Univ. of Hong Kong, China), Yi He, Edwin H.M. Sha (Univ. of Texas, Dallas, U.S.A.)
Page	pp. 879 - 884
Detailed information (abstract, keywords, etc)
Slides

10C-3 (Time: 16:20 - 16:45)

Title	Dynamic and Adaptive Allocation of Applications on MPSoC Platforms.
Author	*Andreas Schranzhofer, Jian-Jia Chen (Swiss Federal Inst. of Tech. (ETH), Zürich, Switzerland), Luca Santinelli (Scuola Superiore Sant'Anna, Pisa, Italy), Lothar Thiele (Swiss Federal Inst. of Tech. (ETH), Zürich, Switzerland)
Page	pp. 885 - 890
Detailed information (abstract, keywords, etc)
Slides

10C-4 (Time: 16:45 - 17:10)

Title	Cool and Save: Cooling Aware Dynamic Workload Scheduling in Multi-socket CPU Systems
Author	Raid Ayoub, *Tajana Rosing (Univ. of California, San Diego, U.S.A.)
Page	pp. 891 - 896
Detailed information (abstract, keywords, etc)
Slides

Session 10D Designers' Forum: Embedded Software Development for Multi-Processor Systems-on-Chip
Time: 15:30 - 17:10 Thursday, January 21, 2010
Location: Room 101D
Organizers: Rainer Doemer (Univ. of California, Irvine, U.S.A.), Andreas Gerstlauer (Univ. of Texas, Austin, U.S.A.)

10D-1 (Time: 15:30 - 15:55)

Title	(Invited Paper) The Shrink Wrapped Myth: Cross Platform Software
Author	*Mike Olivarez (Freescale Semiconductor, Inc., U.S.A.)
Detailed information (abstract, keywords, etc)
Slides

10D-2 (Time: 15:55 - 16:20)

Title	(Invited Paper) Using Software to Achieve Low Power Solutions
Author	*Albert Shiue (Alvaview Technologies, Taiwan)
Detailed information (abstract, keywords, etc)

10D-3 (Time: 16:20 - 16:45)

Title	(Invited Paper) MPSoC Programming using the MAPS Compiler
Author	Rainer Leupers, *Jeronimo Castrillon (RWTH Aachen Univ., Germany)
Page	pp. 897 - 902
Detailed information (abstract, keywords, etc)
Slides

10D-4 (Time: 16:45 - 17:10)

Title	(Invited Paper) System-level Development of Embedded Software
Author	*Gunar Schirner (Northeastern Univ., U.S.A.), Andreas Gerstlauer (Univ. of Texas, Austin, U.S.A.), Rainer Domer (Univ. of California, Irvine, U.S.A.)
Page	pp. 903 - 909
Detailed information (abstract, keywords, etc)
Slides

The 15th Asia and South Pacific Design Automation Conference Technical Program

Session Schedule

List of Papers

The 15th Asia and South Pacific Design Automation Conference
Technical Program